Burst Cycles - Freescale Semiconductor MCF52277 Reference Manual

Figure 18-24 shows a bus cycle using address setup, wait states, and address hold.
FB_CLK
FB_A[23:0]
FB_D[31:X]
FB_R/W
FB_TS
FB_CSn, FB_BE/BWEn
FB_OE
FB_TA
18.4.6

Burst Cycles

The device can be programmed to initiate burst cycles if its transfer size exceeds the port size of the
selected destination. With bursting disabled, any transfer larger than the port size breaks into multiple
individual transfers. With bursting enabled, an access larger than port size results in a burst cycle of
multiple beats. Table 18-8
Port Size PS[1:0]
01 (8-bit)
1x (16-bit)
00 (32-bit)
The FlexBus can support 2-1-1-1 burst cycles to maximize system performance. Delaying termination of
the cycle can add wait states. If internal termination is used, different wait state counters can be used for
the first access and the following beats.
The CSCRn registers enable bursting for reads, writes, or both. Memory spaces can be declared
burst-inhibited for reads and writes by clearing the appropriate CSCRn[BSTR,BSTW] bits.
Freescale Semiconductor
S0 AS
ADDR[31:X]
Figure 18-24. Write Cycle with Two-Clock Address Setup and
Two-Clock Hold (One Wait State)
shows the result of such transfer translations.
Table 18-8. Transfer Size and Port Size Translation
Transfer Size
word
longword
line
longword
line
line
MCF52277 Reference Manual, Rev. 1
S1 WS S2
ADDR[23:0]
DATA
Burst-Inhibited: Number of Transfers
Burst Enabled: Number of Beats
AH S3 S0
2
4
16
2
8
4
FlexBus
18-23