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Address: 0xFC07_0004 (DTRR0)
0xFC07_4004 (DTRR1)
0xFC07_8004 (DTRR2)
0xFC07_C004 (DTRR3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Field
31–0
Reference value compared with the respective free-running timer counter (DTCNn) as part of the output-compare
REF
function.
28.2.5
DMA Timer Capture Registers (DTCRn)
Each DTCRn latches the corresponding DTCNn value during a capture operation when an edge occurs on
DTnIN, as programmed in DTMRn. The internal bus clock is assumed to be the clock source. DTnIN
cannot simultaneously function as a clocking source and as an input capture pin. Indeterminate operation
results if DTnIN is set as the clock source when the input capture mode is used.
Address: 0xFC07_0008 (DTCR0)
0xFC07_4008 (DTCR1)
0xFC07_8008 (DTCR2)
0xFC07_C008 (DTCR3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–0
Captures the corresponding DTCNn value during a capture operation when an edge occurs on DTnIN, as
CAP
programmed in DTMRn.
28.2.6
DMA Timer Counters (DTCNn)
The current value of the 32-bit DTCNs can be read at anytime without affecting counting. Any write to
DTCNn clears it. The timer counter increments on the clock source rising edge (internal bus clock divided
by 1, internal bus clock divided by 16, or DTnIN).
Freescale Semiconductor
REF (32-bit reference value)
Figure 28-5. DTRRn Registers
Table 28-5. DTRRn Field Descriptions
Description
CAP (32-bit capture counter value)
Figure 28-6. DTCRn Registers
Table 28-6. DTCRn Field Descriptions
Description
MCF52277 Reference Manual, Rev. 1
DMA Timers (DTIM0–DTIM3)
Access: User read/write
8
7
6
5
4
3
2
1
0
Access: User read-only
8
7
6
5
4
3
2
1
0
28-7
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