Freescale Semiconductor MCF52277 Reference Manual page 327

Figure 18-27 shows a longword read through an 8-bit device with burst inhibited. The transfer results in
four individual transfers.
There is an extra clock of address setup (AS) for each burst-inhibited
transfer between states S0 and S1.
S0
FB_CLK
FB_A[23:0]
FB_D[31:24]
[31:24]
FB_R/W
FB_TS
FB_CSn, FB_OE
FB_BE/BWEn
FB_TA
Figure 18-27. Longword-Read Burst-Inhibited from 8-Bit Port (No Wait States)
Figure 18-28 shows a longword write through an 8-bit device with burst inhibited. The transfer results in
four individual transfers.
S0
FB_CLK
FB_A[23:0]
ADDR
FB_D[31:24]
[31:24]
FB_R/W
FB_TS
FB_CSn
FB_BE/BWEn
FB_OE
FB_TA
Figure 18-28. Longword-Write Burst-Inhibited to 8-Bit Port (No Wait States)
Freescale Semiconductor
S1 S2
AS S0 AS
ADDR[23:0]
ADDR
DATA
AS S1 S2 S0 AS
ADDR[23:0]
DATA
MCF52277 Reference Manual, Rev. 1
NOTE
S1 S2 S1
S0 AS
ADDR + 1 ADDR + 2
DATA
S1 S2 S0 AS S1
ADDR + 1 ADDR + 2
DATA
S2 S1 S2
S0 AS
ADDR + 3
DATA DATA
DATA
S2 S0 AS S1 S2
ADDR + 3
DATA DATA
DATA
FlexBus
S0
S3
S0
S3
18-25