Freescale Semiconductor MCF52277 Reference Manual page 565

DSync Revision
Version Date
— 31 Oct 2006 E Southers
—
— 02 Nov 2006
—
— 06 Nov 2006
—
— 16 Nov 2006
1.1 12 Jan 2007 E Southers
1.2 19 Jan 2007
1.3 19 Jan 2007
1.4 08 Feb 2007 E Southers
1.5 07 Mar 2007 M Tsurikov
1.6 09 Mar 2007 M Tsurikov
1.7 12 Mar 2007 M Tsurikov
1.8 19 Mar 07
Freescale Semiconductor
Table 24-17. Revision History (continued)
Description of Changes
Author
• Corrected register addresses for DF/ST.
(EDS) Previously added 0x20 offset was
missing from memory map and SDN
register.
M. • Added Kirin2u conditional tag and
Tsurikov assigned it to entries tagged for Kirin.
(MST)
M. • Added Kirin0 conditional tag and
Tsurikov assigned it to entries tagged for Kirin.
(MST)
M. • Added Kirin0u conditional tag and
Tsurikov assigned it to entries tagged for Kirin0.
(MST)
Initial version loaded into DesignSync
(EDS)
M. In the memory map, conditionalized the
Tsurikov SCMISR footnote for DragonFire and
(MST) SuperTarifa (the other parts do not have a
SCMISR).
M.
Tsurikov
(MST)
Added DragonFire0 conditional tag.
(EDS) Applied to same as DF/ST except for bus
speed.
Added missing conditional text for Kirin in
examples.
(MST)
(MST)
(MST)
J Davis Light edit for corrections in grammar, style,
(JMD) punctuation, and formatting.
MCF52277 Reference Manual, Rev. 1
Internal
Kirin2u Rev. 1
Kirin0 Rev. 0 Draft A
Kirin0u Rev. 0 Draft A
Kirin2e Rev. 4
DragonFire0 Rev 0 Draft A (individual chapter PDFs)
Kirin0 Rev 0 Draft B
Kirin0u Rev 0 Draft B
Preparation for Kirin Rev. 3
Kirin Rev. 3
Pulse-Width Modulation (PWM) Module
Description of Changes
External
Previous errata from revision 0 has crept in:
Add a 0x20 offset to all PWM register
addresses in the memory map table.
Register addresses should be from
0xFC09_0020 to 0xFC09_0044.
Also fix address for the PWMSDN register
description to 0xFC09_0044.
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