Freescale Semiconductor MCF52277 Reference Manual page 479

All parameters are defined in pixel periods
LCD_LSCLK periods.
LCD_LSCLK
LCD_HSYNC
LCD_OE
DATA
LCD_VSYNC
Figure 21-42 shows the vertical timing (timing of one frame). The delay from the end of one frame until
the beginning of the next is programmable. The memory timing signal parameters are:
• V_WAIT_1 is a delay measured in lines. For V_WAIT_1= 1 there is a delay of one LCD_HSYNC
(time = one line period) before LCD_VSYNC. The LCD_HSYNC pulse is output during the
V_WAIT_1 delay.
• For V_WIDTH (vertical sync pulse width) = 0, LCD_VSYNC encloses one LCD_HSYNC pulse.
For V_WIDTH = 2, LCD_VSYNC encloses two LCD_HSYNC pulses.
• V_WAIT_2 is a delay measured in lines. For V_WAIT_2 = 1, there is a delay of one LCD_HSYNC
(time = one line period) after LCD_VSYNC. The LCD_HSYNC pulse is output during the
V_WAIT_2 delay.
LCD_VSYNC
LCD_HSYNC
LCD_OE
Freescale Semiconductor
H_WIDTH+1 H_WAIT_2+3
Figure 21-41. Horizontal Sync Pulse Timing in TFT Mode
End of frame
V_WAIT_1
Figure 21-42. Vertical Sync Pulse Timing TFT Mode
MCF52277 Reference Manual, Rev. 1
NOTE
LCD_PCR[PCD]
⎛
-------------------------------------------------- -
⎝
f
sys/2
XMAX
V_WIDTH
(lines)
V_WAIT_2
Liquid Crystal Display Controller (LCDC)
+ 1
⎞
, not
⎠
H_WAIT_1+1
Beginning of frame
YMAX
21-43