Idcode Register - Freescale Semiconductor MCF52277 Reference Manual

33.3.2

IDCODE Register

The IDCODE is a read-only register; its value is chip dependent. For more information, see
Section 33.4.3.1, "IDCODE
IR[4:0]: 0_0001 (IDCODE)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
R PRN
W
1
Reset See note
1
The reset values for PRN and PIN are device-dependent.
Field
31–28 Part revision number. Indicate the revision number of the device.
PRN
27–22 Freescale Design Center number.
DC
21–12 Part identification number. Indicate the device number.
PIN 0x06C MCF52277
0x06E MCF52274
11–1 Joint Electron Device Engineering Council ID bits. Indicate the reduced JEDEC ID for Freescale (0x0E).
JEDEC
0 IDCODE register ID. This bit is set to 1 to identify the register as the IDCODE register and not the bypass register
ID according to the IEEE standard 1149.1.
33.3.3 Bypass Register
The bypass register is a single-bit shift register path from TDI to TDO when the BYPASS, CLAMP, or
HIGHZ instructions are selected. After entry into the capture-DR state, the single-bit shift register is set to
a logic 0. Therefore, the first bit shifted out after selecting the bypass register is always a logic 0.
33.3.4 TEST_CTRL Register
The TEST_CTRL register is a 1-bit shift register path from TDI to TDO when the
ENABLE_TEST_CTRL instruction is selected. The TEST_CTRL transfers its value to a parallel hold
register on the rising edge of TCLK when the TAP state machine is in the update-DR state. The DSE bit
selects the drive strength used in JTAG mode.
Freescale Semiconductor
Instruction".
DC
0 1 1 1 0 1
Figure 33-3. IDCODE Register
Table 33-4. IDCODE Field Descriptions
MCF52277 Reference Manual, Rev. 1
PIN
1
See note 0 0 0 0 0 0 0 1 1 1 0 1
Description
IEEE 1149.1 Test Access Port (JTAG)
Access: User read-only
9 8 7 6 5 4 3 2
JEDEC
1 0
ID
33-5