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Pulse-Width Modulation (PWM) Module
Field
1
PWM Channel 1 Output Enable. If enabled, the PWM signal becomes available at PWMOUT1 when its
PWME1
corresponding clock source begins its next cycle.
0 PWM output disabled
1 PWM output enabled
0
Reserved, must be cleared.
24.2.2
PWM Polarity Register (PWMPOL)
The starting polarity of each PWM channel waveform is determined by the associated PWMPOL[PPOLn]
bit. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can
occur during the transition.
Address: 0xFC09_0021 (PWMPOL)
7
R
PPOL7
W
Reset:
0
Field
7,5,3,1
PWM channel n polarity.
PPOLn
0 PWM channel n output is low at the beginning of the period, then goes high when the duty count is reached
1 PWM channel n output is high at the beginning of the period, then goes low when the duty count is reached
6,4,2,0
Reserved, must be cleared.
24.2.3
PWM Clock Select Register (PWMCLK)
Each PWM channel has the capability of selecting one of two clocks. For channels 1 and 5, the clock
choices are clock A or SA. For channels 3 and 7, the choices are clock B or SB. The clock selection is done
with the below PWMCLK[PCLKn] control bits. If a clock select is changed while a PWM signal is being
generated, a truncated or stretched pulse can occur during the transition.
Address: 0xFC09_0022 (PWMCLK)
7
R
PCLK7
W
Reset:
0
24-4
Table 24-2. PWME Field Descriptions (continued)
6
5
0
PPOL5
0
0
Figure 24-3. PWM Polarity Register (PWMPOL)
Table 24-3. PWMPOL Field Descriptions
6
5
0
PCLK5
0
0
Figure 24-4. PWM Clock Select Register (PWMCLK)
MCF52277 Reference Manual, Rev. 1
Description
4
3
0
PPOL3
0
0
Description
4
3
0
PCLK3
0
0
Access: User Read/Write
2
1
0
PPOL1
0
0
Access: User Read/Write
2
1
0
PCLK1
0
0
Freescale Semiconductor
0
0
0
0
0
0
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