Page Management - Freescale Semiconductor MCF52277 Reference Manual

8. Initialize the SDRAM's mode register and reset the DLL using the
Section 19.5.1.6, "Load Mode/Extended Mode Register Command (lmr, lemr),"
instruction on issuing a
should be set to normal operation/reset DLL.
9. Pause for the DLL lock time specified by the memory.
10. Issue a second
PALL
set. The SDCR[REF and IREF] bits should remain cleared for this step.
11. Refresh the SDRAM. The SDRAM specification should indicate many refresh cycles performed
before issuing an
IPALL] must be cleared). This forces a refresh of the SDRAM each time the IREF bit is set. Repeat
this step until the specified number of refresh cycles have been completed.
12. Initialize the SDRAM's mode register using the
Mode/Extended Mode Register Command (lmr, lemr),"
command. During this step the OP_MODE field of the mode register should be set to normal
operation.
13. Set SDCR[REF] to enable automatic refreshing, and clear SDCR[MODE_EN] to lock the SDMR.
SDCR[IREF and IPALL] remain cleared.
19.6.1

Page Management

SDRAM devices have four internal banks. A particular row and bank of memory must be activated to
allow read and write accesses. The SDRAM controller supports paging mode to maximize the memory
access throughout. During operation, the SDRAM controller maintains an open page for each SD_CS
block. An open page is composed of the active rows in the internal banks. Each internal bank has its own
active row.
The physical page size of a SD_CS block is equal to the space size divided by the number of rows; but the
page may not be contiguous in the internal address space because SDRAMs can have a different row
address open in each bank and the internal address bits (A[27:24] and A[9:2]) or (A[27:24] and A[9:1])
used for memory column addresses are not consecutive.
Because the column address may split across two portions of the internal address, the contiguous page size
is (number of contiguous columns per bank) × (number of bits). This gives a contiguous page size of
1 KBytes. However, the total (possibly fragmented) page size is (number of banks) × (number of
columns) × (number of bits).
If a new access does not fall in the open row of an open bank of a SD_CS block, the open row must be
closed ( ) and the new row must be opened (
PRE
command activates only one bank at one time. If another read or write falls in an inactive bank,
ACTV
another is needed, but no precharge is needed. If a read or write falls in any open row of any active
ACTV
banks of a page, no
PRE
A page is kept open until one of the following conditions occurs:
• An access outside the open page.
• A refresh cycle is started.
Freescale Semiconductor
command. During this step the OP_MODE field of the mode register
LMR
command. Initialize the SDRAM control register (SDCR) with SDCR[IPALL]
command. Write to the SDCR with the IREF bit set (SDCR[REF and
LMR
or is needed; the read or write command can be issued immediately.
ACTV
MCF52277 Reference Manual, Rev. 1
command. See
LMR
for more instruction on issuing an
), then the or
ACTV READ
SDRAM Controller (SDRAMC)
command. See
LMR
for more
Section 19.5.1.6, "Load
command can proceed. An
WRITE
LMR
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