Freescale Semiconductor MCF52277 Reference Manual page 354

SDRAM Controller (SDRAMC)
A precharge is required after DRAMs also have a maximum bank-open
period. The memory controller does not time the bank-open period because
the refresh interval is always less.
19.5.1.6 Load Mode/Extended Mode Register Command (
All SDRAM devices contain mode registers that configure the timing and burst mode for the SDRAM.
These commands access the mode registers that physically reside within the SDRAM devices. During the
or command, SDRAM latches the address and bank buses to load the values into the selected
LMR LEMR
mode register.
The
LMR
Use the following steps to write the mode register and extended mode register:
1. Set the SDCR[MODE_EN] bit.
2. Write the SDMR[BA] bits to select the mode register.
3. Write the desired mode register value to the SDMR[ADDR]. Do not overwrite the SDMR[BA]
values. This step can be performed in the same register write in step 2.
4. Set the SDMR[CMD] bit.
5. For DDR, step 2 to 4 should be performed twice. The first is for the extended-mode register, and
the last is for the mode register.
6. Clear the SDCR[MODE_EN] bit.
19.5.1.6.1 Mode Register Definition
Figure 19-10 shows the mode register definition. This is the SDRAM's mode register, not the SDRAMC's
mode/extended mode register (SDMR) defined in
Register (SDMR)." Refer to device data sheet for detailed description.
BA1 BA0
Field 0
Field
BA1–BA0 Bank address. These must be zero to select the mode register.
A11–A7 Operating mode.
OP_MODE xx000 Standard Operation (SDR only)
00000 Normal Operation (DDR)
00010 Reset DLL (DDR)
Else Reserved
A6–A4 CAS latency. Delay in clocks from issuing a
CL because the CL settings supported can vary from memory to memory.
19-24
and commands are only used during SDRAM initialization.
LEMR
A11 A10 A9
0 OP_MODE
Figure 19-10. Mode Register
Table 19-13. Mode Register Field Descriptions
MCF52277 Reference Manual, Rev. 1
NOTE
NOTE
Section 19.4.1, "SDRAM Mode/Extended Mode
A8 A7 A6 A5
CL
Description
to valid data out. Check the SDRAM manufacturer's spec
READ
, )
LMR LEMR
A4 A3 A2 A1
BT BLEN
Freescale Semiconductor
A0