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Field
7–6
Port size. Specifies the data port width associated with each chip-select. It determines where data is driven during
PS
write cycles and where data is sampled during read cycles.
00 32-bit port size. Valid data sampled and driven on FB_D[31:0]
01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if SBM = 0 or FB_D[7:0] if SBM = 1
1x 16-bit port size. Valid data sampled and driven on FB_D[31:16] if SBM = 0 or FB_D[15:0] if SBM = 1
5
Byte-enable mode. Specifies the byte enable operation. Certain memories have byte enables that must be asserted
BEM
during reads and writes. BEM can be set in the relevant CSCR to provide the appropriate mode of byte enable
support for these SRAMs.
0 FB_BE/BWE is not asserted for reads. FB_BE/BWE is asserted for data write only.
1 FB_BE/BWE is asserted for read and write accesses.
4
Burst-read enable. Specifies whether burst reads are used for memory associated with each FB_CSn.
BSTR
0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a
longword read from an 8-bit port is broken into four 8-bit reads.
1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports,
word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports.
3
Burst-write enable. Specifies whether burst writes are used for memory associated with each FB_CSn.
BSTW
0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword
write to an 8-bit port takes four byte writes.
1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word
writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
2–0
Reserved, must be cleared.
18.4
Functional Description
18.4.1
Chip-Select Operation
Each chip-select has a dedicated set of registers for configuration and control:
•
Chip-select address registers (CSARn) control the base address space of the chip-select. See
Section 18.3.1, "Chip-Select Address Registers (CSAR0–CSAR5)."
•
Chip-select mask registers (CSMRn) provide 16-bit address masking and access control. See
Section 18.3.2, "Chip-Select Mask Registers (CSMR0–CSMR5)."
•
Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state
generation, address setup and hold times, and automatic acknowledge generation features. See
Section 18.3.3, "Chip-Select Control Registers (CSCR0–CSCR5)."
FB_CS0 is a global chip-select after reset and provides re-locatable boot ROM capability.
Freescale Semiconductor
Table 18-5. CSCRn Field Descriptions (continued)
MCF52277 Reference Manual, Rev. 1
Description
FlexBus
18-9
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