Freescale Semiconductor MCF52277 Reference Manual page 748

Debug Module
Field
31–28 Breakpoint Status. Provides read-only status (from the BDM port only) information concerning hardware
BSTAT breakpoints. BSTAT is cleared by a TDR write or by a CSR read when a level-2 breakpoint is triggered or a level-1
breakpoint is triggered and the level-2 breakpoint is disabled.
0000 No breakpoints enabled
0001 Waiting for level-1 breakpoint
0010 Level-1 breakpoint triggered
0101 Waiting for level-2 breakpoint
0110 Level-2 breakpoint triggered
27 Fault-on-fault. If FOF is set, a catastrophic halt occurred and forced entry into BDM. FOF is cleared when CSR is
FOF read (from the BDM port only).
26 Hardware breakpoint trigger. If TRG is set, a hardware breakpoint halted the processor core and forced entry into
TRG BDM. Reset, the debug
25 Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM. Reset, the debug
HALT command, or reading CSR (from the BDM port only) clear HALT.
24 Breakpoint assert. If BKPT is set, BKPT was asserted, forcing the processor into BDM. Reset, the debug
BKPT command, or reading CSR (from the BDM port only) clear BKPT.
23–20 Hardware revision level. Indicates, from the BDM port only, the level of debug module functionality. An emulator
HRL could use this information to identify the level of functionality supported.
0000 Revision A
0001 Revision B
0010 Revision C
0011 Revision D
1001 Revision B+ (This is the value used for this device)
1011 Revision D+
19 Reserved, must be cleared.
18 Breakpoint disable. Disables the normal BKPT input signal functionality, and allows the assertion of this pin to
BKD generate a debug interrupt.
0 Normal operation
1 BKPT is edge-sensitive: a high-to-low edge on BKPT signals a debug interrupt to the ColdFire core. The
processor makes this interrupt request pending until the next sample point occurs, when the exception is
initiated. In the ColdFire architecture, the interrupt sample point occurs once per instruction. There is no
support for nesting debug interrupts.
17 PSTCLK disable.
PCD 0 PSTCLK is fully operational
1 Disables the generation of the PSTCLK and PSTDDATA output signals, and forces these signals to remain
quiescent
16 Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module's programming model
IPW registers. Only commands from the external development system can modify IPW.
15 Force processor references in emulator mode.
MAP 0 All emulator-mode references are mapped into supervisor code and data spaces.
1 The processor maps all references while in emulator mode to a special address space, TT equals 10,
TM equals 101 or 110. The internal SRAM and caches are disabled.
14 Force emulation mode on trace exception.
TRC 0 The processor enters supervisor mode
1 The processor enters emulator mode when a trace exception occurs
32-8
Table 32-6. CSR Field Descriptions
Description
command or reading CSR (from the BDM port only) clear TRG.
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