Freescale Semiconductor MCF52277 Reference Manual page 318

FlexBus
Figure 18-11 shows the similar configuration for a write transfer. The data is driven from the second clock
on FB_D[31:24].
FB_CSn, FB_BE/BWEn
Figure 18-12 illustrates the basic word read transfer to a 16-bit device with no wait states. The address is
driven on the FB_A[ 23:8
FB_D[31:16], and may tristate the data line or continue driving the data one clock after FB_TA is sampled
asserted.
18-16
S0
FB_CLK
FB_A[23:0]
FB_D[31:24]
ADDR[31:24]
FB_R/W
FB_TS
FB_OE
FB_TA
Figure 18-11. Single Byte-Write Transfer
:0] bus throughout the bus cycle. The external device returns the read data on
S0
FB_CLK
FB_A[23:0]
ADDR[31:16]
FB_D[31:16]
FB_R/W
FB_TS
FB_CSn, FB_OE
FB_BE/BWEn
FB_TA
Figure 18-12. Single Word-Read Transfer
MCF52277 Reference Manual, Rev. 1
S1 S2 S3
ADDR[23:0]
DATA[7:0]
S1 S2 S3
ADDR[23:0]
DATA[15:0]
S0
S0
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