Introduction - Freescale Semiconductor MCF52277 Reference Manual

Chapter 19
SDRAM Controller (SDRAMC)
19.1

Introduction

This chapter describes configuration and operation of the synchronous DRAM (SDRAM) controller. It
begins with a general description and brief glossary and includes a description of signals involved in
DRAM operations. The remainder of the chapter describes the programming model and signal timing, as
well as the command set required for synchronous operations. It also includes examples to better
understand how to configure the DRAM controller for synchronous operations.
Unless otherwise noted, in this chapter clock refers to the system clock
(f ).
sys/2
The external data bus is shared between the FlexBus module and the
SDRAM controller. When the SDRAM controller is in SDR mode, the data
bus is switched dynamically between the SDRAM controller and the
FlexBus module. However, when the SDRAM controller is in DDR mode,
D[31:16] is dedicated to the SDRAM data bus and D[15:0] is dedicated to
the FlexBus data bus.
Freescale Semiconductor
NOTE
MCF52277 Reference Manual, Rev. 1
19-1