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Static RAM (SRAM)
6.2
Memory Map/Register Description
The SRAM programming model shown in
register (RAMBAR), SRAM initialization, and power management.
1
Rc[11:0]
0xC05
RAM Base Address Register (RAMBAR)
1
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see
Chapter 32, "Debug Module."
6.2.1
SRAM Base Address Register (RAMBAR)
The configuration information in the SRAM base-address register (RAMBAR) controls the operation of
the SRAM module.
•
The RAMBAR holds the SRAM base address. The MOVEC instruction provides write-only access
to this register.
•
The RAMBAR can be read or written from the debug module.
•
All undefined bits in the register are reserved. These bits are ignored during writes to the
RAMBAR and return zeroes when read from the debug module.
•
A reset clears the RAMBAR's priority, backdoor write-protect, and valid bits, and sets the
backdoor enable bit. This enables the backdoor port and invalidates the processor port to the
SRAM (The RAMBAR must be initialized before the core can access the SRAM.) All other bits
are unaffected.
The only applicable address ranges for the SRAM module's base address are
0x8000_0000–0x8FFE_0000. The adress must be 0-modulo-128 K. Set the
RAMBAR register appropriately.
By default, the RAMBAR is invalid, but the backdoor is enabled. In this
state, any core accesses to the SRAM are routed through the backdoor.
Therefore, the SRAM is accessible by the core, but it does not have a
single-cycle access time. To ensure that the core has single-cycle access to
the SRAM, set the RAMBAR[V] bit.
Any access within the memory range allocated for the on-chip SRAM
(0x8000_0000-0x8FFF_FFFF) hits in the SRAM even if the address is
beyond the defined size for the SRAM. This creates address aliasing for the
on-chip SRAM memory. For example, writes to addresses 0x8000_0000
and 0x8002_0000 modify the same memory location. System software
should ensure SRAM address pointers do not exceed the SRAM size to
prevent unwanted overwriting of SRAM.
6-2
Table 6-1
Table 6-1. SRAM Programming Model
Register
Supervisor Access Only Registers
NOTE
MCF52277 Reference Manual, Rev. 1
includes a description of the SRAM base address
Width
Access
Reset Value
(bits)
32
R/W
See Section
Written
Section/Page
w/ MOVEC
Yes
6.2.1/6-2
Freescale Semiconductor
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