Freescale Semiconductor MCF52277 Reference Manual page 661

Field
21–20 After SCK delay prescaler. Selects the prescaler value for the delay between the last edge of DSPI_SCK and the
PASC negation of DSPI_PCS. This field is only used in master mode. The ASC field description in
to compute the after SCK delay.
00 1 clock delay between last edge of DSPI_SCK and DSPI_PCS negation prescaler
01 3 clock delay between last edge of DSPI_SCK and DSPI_PCS negation prescaler
10 5 clock delay between last edge of DSPI_SCK and DSPI_PCS negation prescaler
11 7 clock delay between last edge of DSPI_SCK and DSPI_PCS negation prescaler
19–18 Delay after transfer prescaler. The PDT field selects the prescaler value for the delay between the negation of the
PDT DSPI_PCS signal at the end of a frame and the assertion of DSPI_PCS at the beginning of the next frame. The PDT
field is only used in master mode. The DT field description in
transfer.
00 1 clock delay between negation of DSPI_PCS to assertion of next DSPI_PCS prescaler
01 3 clock delay between negation of DSPI_PCS to assertion of next DSPI_PCS prescaler
10 5 clock delay between negation of DSPI_PCS to assertion of next DSPI_PCS prescaler
11 7 clock delay between negation of DSPI_PCS to assertion of next DSPI_PCS prescaler
17–16 Baud rate prescaler. Selects the prescaler value for the baud rate. This field is only used in master mode. The baud
PBR rate is the frequency of the serial communications clock (DSPI_SCK). The system clock is divided by the prescaler
value before the baud rate selection takes place. The description for
how to compute the baud rate.
00 2 clock prescaler to divide system clock
01 3 clock prescaler to divide system clock
10 5 clock prescaler to divide system clock
11 7 clock prescaler to divide system clock
15–12 PCS to SCK delay scaler. Selects the scaler value for the PCS to SCK delay. This field is only used in master mode.
CSSCK The PCS to SCK delay is the delay between the assertion of DSPI_PCS and the first edge of the DSPI_SCK. The
table below lists the scaler values.
Note: When the continuous selection format is selected (CONT or DCONT is set), switching the PCS to SCK delay
prescaler without stopping the DSPI can cause errors in the transfer.
Note: See Section 29.4.3.2, "PCS to SCK Delay
Freescale Semiconductor
Table 29-5. DSPI_CTARn Field Description (continued)
PCS to SCK Delay
CSSCK
Scaler Value
0000 2
0001 4
0010 8
0011 16
0100 32
0101 64
0110 128
0111 256
MCF52277 Reference Manual, Rev. 1
Description
Table 29-5 explains how to compute the delay after
Section 29.4.3.1, "Baud Rate
PCS to SCK Delay
CSSCK
1000
1001
1010
1011
1100
1101
1110
1111
(tCSC)," for details on calculating the PCS to SCK delay.
DMA Serial Peripheral Interface (DSPI)
Table 29-5 explains how
Generator" details
Scaler Value
512
1024
2048
4096
8192
16384
32768
65536
29-11