Table of Contents
Advertisement
— 11 bit row address (RA), 9 bit column address (CA), 2 bit bank address (BA), 16-bit bus,
one chip select
•
Supports up to 512 MByte of memory.
— 24/25 bits RA+CA, 2 bits BA, 32/16-bit bus, two chip selects
•
Supports page mode for decreased latency and higher bandwidth; remembers one active row for
each bank; four independent active rows per each chip select.
•
Programmable refresh interval timer.
•
Supports sleep mode and self-refresh mode.
•
Error detect and parity check are not supported.
•
The SDRAM controller does not include a dedicated I
(DIMM) serial presence detect EEPROM. If needed, this must be managed by one of the on-chip
2
I
C channels external to the SDRAM controller.
19.1.3
Terminology
The following terminology is used in this chapter:
•
SDRAM block: Any group of DRAM memories selected by one of the SD_CS signals. Therefore,
the SDRAMC can support up to two independent memory blocks. The base address of each block
is programmed in the SDRAM chip-select configuration registers.
•
SDRAM bank: An internal partition in an SDRAM device. For example, a 64-Mbit SDRAM
component might be configured as four 512K x 32 banks. Banks are selected through the
SD_BA[1:0] signals.
•
SDRAM: RAMs that operate like asynchronous DRAMs but with a synchronous clock, a
pipelined, multiple-bank architecture, and a faster speed.
19.2
External Signal Description
This section introduces the signal names used in this chapter.
Signal
I/O
SD_A[13:0]
O Memory multiplexed row/column address. Provides the row address for
address and auto-precharge bit for
in the respective bank. A10 is sampled during a precharge command to determine whether the precharge
applies to one bank (A10 negated) or all banks (A10 asserted). If only one bank is to be precharged, the
bank is selected by SD_BA[1:0].
The address outputs also provide the opcode during a MODE REGISTER SET command. SD_BA[1:0]
signals define which mode register is loaded during the MODE REGISTER SET (MRS). A12 is used on
device densities of 256 Mb and above.
Timing
SD_BA[1:0]
O Memory bank address. Define which bank an
applied. It is also used to select the SDRAM internal mode register during power-up initialization.
Timing
Freescale Semiconductor
Table 19-1. SDRAM Interface—Detailed Signal Descriptions
Assertion/Negation — Occurs synchronously with SD_CLK
Assertion/Negation — Occurs synchronously with SD_CLK
MCF52277 Reference Manual, Rev. 1
2
C interface to access memory module
Description
/
commands, to select one location out of the memory array
READ
WRITE
,
,
ACTV
READ
WRITE
SDRAM Controller (SDRAMC)
commands, and the column
ACTV
, or PRECHARGE command is being
19-3
Advertisement
Table of Contents
