Freescale Semiconductor MCF52277 Reference Manual page 379

Field
12 Host controller halted. This bit is cleared when the USBCMD[RS] bit is set. The controller sets this bit after it
HCH stops executing because of the USBCMD[RS] bit being cleared, by software or the host controller hardware (for
example, internal error). Used only in host mode.
0 Running.
1 Halted.
11–9 Reserved, must be cleared.
8 Device-controller suspend. Non-EHCI bit. When a device controller enters a suspend state from an active state,
SLI this bit is set. The device controller clears the bit upon exiting from a suspend state. Used only by the device
controller.
0 Active.
1 Suspended.
7 SOF received. This is a non-EHCI status bit. Software writes a 1 to this bit to clear it.
SRI Host mode:
In host mode, this bit is set every 125 μs, provided PHY clock is present and running (for example, the port
is NOT suspended) and can be used by the host-controller driver as a time base.
Device mode:
When controller detects a start of (micro) frame, bit is set. When a SOF is extremely late, controller
automatically sets this bit to indicate an SOF was expected. Therefore, this bit is set roughly every 1 ms in
device FS mode and every 125 μsec in HS mode, and it is synchronized to the actual SOF received.
Because the controller is initialized to FS before connect, this bit is set at an interval of 1 ms during the
prelude to the connect and chirp.
6 USB reset received. A non-EHCI bit. When the controller detects a USB reset and enters the default state, this
URI bit is set. Software can write a 1 to this bit to clear it. Used only by in device mode.
0 No reset received.
1 Reset received.
5 Interrupt on async advance. By setting the USBCMD[IAA] bit, system software can force the controller to issue
AAI an interrupt the next time the controller advances the asynchronous schedule. This status bit indicates the
assertion of that interrupt source. Used only by the host mode.
0 No async advance interrupt.
1 Async advance interrupt.
4 System error. Set when an error is detected on the system bus. If the system error enable bit (USBINTR[SEE])
SEI is set, interrupt generates. The interrupt and status bits remain set until cleared by writing a 1 to this bit.
Additionally, when in host mode, the USBCMD[RS] bit is cleared, effectively disabling controller. An interrupt
generates for the USB OTG controller in device mode, but no other action is taken.
0 Normal operation
1 Error
3 Frame-list rollover. Controller sets this bit when the frame list index (FRINDEX) rolls over from its maximum
FRI value to 0. The exact value the rollover occurs depends on the frame list size. For example, if the frame list size
(as programmed in the USBCMD[FS] field) is 1024, the frame index register rolls over every time FRINDEX[13]
toggles. Similarly, if the size is 512, the controller sets this bit each time FRINDEX[12] toggles. Used only in the
host mode.
Freescale Semiconductor
Table 20-20. USBSTS Field Descriptions (continued)
MCF52277 Reference Manual, Rev. 1
Universal Serial Bus Interface – On-The-Go Module
Description
20-21