Memory Map/Register Definition - Freescale Semiconductor MCF52277 Reference Manual

which is indicated by the PST marker value immediately preceding the DDATA nibble that begins the data
output.
Multiple byte DDATA values are displayed in least-to-most-significant order. The processor captures only
those target addresses associated with taken branches that use a variant addressing mode, or RTE and RTS
instructions, JMP and JSR instructions using address register indirect or indexed addressing modes, and
all exception vectors.
The simplest example of a branch instruction using a variant address is the compiled code for a C language
case statement. Typically, the evaluation of this statement uses the variable of an expression as an index
into a table of offsets, where each offset points to a unique case within the structure. For such
change-of-flow operations, the ColdFire processor uses the debug pins to output the following sequence
of information on two successive processor clock cycles:
1. Use PST (0x5) to identify that a taken branch is executed.
2. Using the PST pins, optionally signal the target address to be displayed sequentially on the DDATA
pins. Encodings 0x9–0xB identify the number of bytes displayed.
3. The new target address is optionally available on subsequent cycles using the DDATA port. The
number of bytes of the target address displayed on this port is configurable (2, 3, or 4 bytes, where
the encoding is 0x9, 0xA, and 0xB, respectively).
Another example of a variant branch instruction would be a JMP (A0) instruction.
PST and DDATA outputs that indicate a JMP (A0) execution, assuming the CSR was programmed to
display the lower 2 bytes of an address.
PSTCLK
PST
DDATA
PST of 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. Therefore, the
subsequent 4 nibbles of DDATA display the lower two bytes of address register A0 in
least-to-most-significant nibble order. The PST output after the JMP instruction completes depends on the
target instruction. The PST can continue with the next instruction before the address has completely
displayed on DDATA because of the DDATA FIFO. If the FIFO is full and the next instruction has captured
values to display on DDATA, the pipeline stalls (PST = 0x0) until space is available in the FIFO.
32.4

Memory Map/Register Definition

In addition to the existing BDM commands that provide access to the processor's registers and the memory
subsystem, the debug module contain a number of registers to support the required functionality. These
registers are also accessible from the processor's supervisor programming model by executing the
WDEBUG instruction (write only). Therefore, the breakpoint hardware in debug module can be read or
Freescale Semiconductor
0x5 0x9
0x0 0x0
Figure 32-2. Example JMP Instruction Output on PST/DDATA
MCF52277 Reference Manual, Rev. 1
default default
A[3:0] A[7:4]
Figure 32-2
default default
A[11:8] A[15:12]
Debug Module
shows the
32-5