Freescale Semiconductor MCF52277 Reference Manual page 413

20.5.3.2 Port State and Control
From a chip or system reset, the USB OTG module enters the powered state. A transition from the powered
state to the attach state occurs when the USBCMD[RS] bit is set. After receiving a reset on the bus, the
port enters the defaultFS or defaultHS state in accordance with the protocol reset described in Appendix
C.2 of the Universal Serial Bus Specification, Revision 2.0.
device.
Power
Interruption
When the host
resets, the device
returns to the
default state.
States powered, attach, defaultFS/HS, suspendFS/HS are implemented in the USB OTG, and they are
communicated to the DCD using these status bits:
Freescale Semiconductor
Active State
Powered
Attach
Default
FS/HS
Address
Assigned
Address
FS/HS
Device
De-configured
Configured
FS/HS
Software-only state
Figure 20-41. USB 2.0 Device States
MCF52277 Reference Manual, Rev. 1
Universal Serial Bus Interface – On-The-Go Module
Figure 20-41
Inactive State
Set Run/Stop bit
to run mode
Reset
Bus Inactive
Suspend
FS/HS
Bus Activity
Bus Inactive
Suspend
FS/HS
Bus Activity
Device
Configured
Bus Inactive
Suspend
FS/HS
Bus Activity
depicts the state of a USB 2.0
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