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Signal Descriptions
Table 2-17. DMA Serial Peripheral Interface (DSPI) Signals (continued)
Signal Name
Synchronous Serial Data
Input
Serial Clock
Peripheral Chip Selects
Peripheral Chip Select 0/
Slave Select
2.3.16
UART Module Signals
Table 2-18
describes the signals of the three UART modules, where n equals 0–2. Baud-rate clock inputs
are not supported.
Signal Name
Transmit Serial Data
Output
Receive Serial Data
Input
Request-to-Send
Clear-to-Send
2.3.17
Synchronous Serial Interface (SSI) Signals
Signal Name
Serial Bit Clock
Serial Master Clock
2-12
Abbreviation
DSPI_SIN
Provides the serial data to the DSPI, which may be sampled on the
rising or falling edge of DSPI_SCK. Each byte is written to RAM lsb
first.
DSPI_SCK
Provides the serial clock from the DSPI. In master mode, the
processor generates DSPI_SCK; in slave mode, DSPI_SCK is an
input from an external bus master.
DSPI_PCS[4,2] Provide DSPI peripheral chip selects, which may be active high or low.
DSPI_PCS0/
In master mode, DSPI_PCS0 is a peripheral chip select output that
DSPI_SS
selects which slave device the current transmission is intended.
In slave mode, the SS signal is a slave select input that an SPI master
uses to select the processor as the target for transmission.
Table 2-18. UART Module Signals
Abbreviation
UnTXD
Data is shifted out lsb first at the falling edge of the serial clock source.
Output is held high when transmitter is disabled, idle, or in local
loopback mode.
UnRXD
Data is sampled Isb first at the serial clock source's rising edge. When
the UART clock is stopped for power-down mode, any transition on this
pin restarts it.
UnRTS
Automatic request-to-send outputs from UART modules. They may
also be asserted and negated as a function of the received FIFO level.
UnCTS
Indicates UART modules can begin data transmission
Table 2-19. SSI Module Signals
Abbreviation
SSI_BCLK
Used by the receive and transmit blocks. In gated clock mode,
SSI_BCLK is only valid during transmission of data; otherwise it is
pulled to an inactive state.
SSI_MCLK
This clock signal is output from the device when it is the master. When
2
in I
S master mode, this signal is referred to as the oversampling
clock. The frequency of SSI_MCLK is a multiple of the frame clock.
MCF52277 Reference Manual, Rev. 1
Function
Function
Function
Freescale Semiconductor
I/O
I
I/O
O
I/O
I/O
O
I
O
I
I/O
I/O
O
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