Dma Timer Reference Registers (Dtrrn) - Freescale Semiconductor MCF52277 Reference Manual

DMA Timers (DTIM0–DTIM3)
Field
7–2 Reserved, must be cleared.
1 Output reference event. The counter value, DTCNn, equals the reference value, DTRRn. Writing a 1 to REF clears
REF the event condition. Writing a 0 has no effect.
0 Capture event. The counter value has been latched into DTCRn. Writing a 1 to CAP clears the event condition.
CAP Writing a 0 has no effect.
28.2.4

DMA Timer Reference Registers (DTRRn)

Each DTRRn, shown in
free-running timer counter (DTCNn) as part of the output-compare function. The reference value is not
matched until DTCNn equals DTRRn, and the prescaler indicates that DTCNn should be incremented
again. Therefore, the reference register is matched after DTRRn + 1 time intervals.
28-6
Table 28-4. DTERn Field Descriptions
REF DTMRn[ORRI]
0 X
1 0
1 0
1 1
1 1
DTXMRn
CAP DTMRn[CE]
[DMAEN]
0 XX
1 00
1 00
1 01
1 01
1 10
1 10
1 11
1 11
Figure 28-5, contains the reference value compared with the respective
MCF52277 Reference Manual, Rev. 1
Description
DTXMRn[DMAEN]
X
0
1
0 Interrupt request asserted
1 DMA request asserted
X No event
0 Disable capture event output
1 Disable capture event output
0 Capture on rising edge & trigger interrupt
1 Capture on rising edge & trigger DMA
0 Capture on falling edge & trigger interrupt
1 Capture on falling edge & trigger DMA
0 Capture on any edge & trigger interrupt
1 Capture on any edge & trigger DMA
No event
No request asserted
No request asserted
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