Chapter 29
DMA Serial Peripheral Interface (DSPI)
29.1
Introduction
This chapter describes the DMA serial peripheral interface (DSPI), which provides a synchronous serial
bus for communication between the MCU and an external peripheral device.
29.1.1
Block Diagram
Figure 29-1
shows a block diagram of the DSPI.
eDMA
DMA and Interrupt Control
TX FIFO
CMD
TX Data
Baud Rate,
Delay and Transfer
Control
29.1.2
Overview
The DMA serial peripheral interface (DSPI) block provides a synchronous serial bus for communication
between an MCU and an external peripheral device. The DSPI supports up to 32 queued SPI transfers (16
receive and 16 transmit) in the DSPI resident FIFOs eliminating CPU intervention between transfers.
Freescale Semiconductor
INTC
RX FIFO
RX Data
16
16
Shift Register
Figure 29-1. DSPI Block Diagram
MCF52277 Reference Manual, Rev. 1
Internal Bus
DSPI BIU
2
DSPI_SOUT
DSPI_SIN
DSPI_SCK
DSPI_PCS0/SS
DSPI_PCS[2,4]
29-1