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The PCR[OUTDIVn] fields can be changed during normal operation or when the device is in limp mode.
However, PCR[PFDR] can only be altered during limp mode. After a new value is written to the PCR, the
PLL synchronizes the new value of the PCR with the VCO clock domain. Then, the transition from the old
divider value to the new divider value takes place, such that the PLL output clocks remain glitch free.
During the adjustment to the new divider value, a PLL output clock may experience an intermediate
transition while the divider values are being synchronized. Following the transition period, all output
clocks begin toggling at the new divider values simultaneously. The transition from the old divider value
to the new divider value takes no more than 100 ns. Because the output divider transition takes a period of
time to change, the PCR may not be written back-to-back without waiting 100 ns between writes.
7.3.2
Lock Conditions
The lock-detect logic monitors the reference frequency and the PLL feedback frequency to determine
when frequency lock has been achieved. Phase lock is inferred by the frequency relationship, but is not
guaranteed. The PLL lock status reflects in the PSR[LOCK] status bit. The lock-detect function uses two
counters clocked by the reference and PLL feedback, respectively. When the reference counter has counted
N cycles, the feedback counter is compared. If the feedback counter has also counted N cycles, the process
is repeated for N + K counts. Then, if the two counters counts continue to match, the lock criteria relaxes
by one count, and the system is notified that the PLL has achieved frequency lock by setting the
PSR[LOCK] bit.
After detection of lock, the lock circuitry continues monitoring the reference and feedback frequencies
using the alternate count and compare process. If the counters do not match at any comparison time, then
the PSR[LOCK] and PSR[LOCKS] status bits are cleared to indicate the PLL has lost lock. At this point,
the lock criteria tightens and the lock detect process repeats. The alternate count sequences prevent false
lock detects due to frequency aliasing while the PLL tries to lock. Alternating between a tight and relaxed
lock criteria prevents the lock detect function from randomly toggling between locked and not locked
status due to phase sensitivities.
In PLL bypass mode, the PSR[LOCK] bit is set 16 clock cycles after reset as described above. In this case,
the signal does not indicate the PLL has locked to the input reference, but the bypass clock is present on
the output. In bypass mode, no PLL lock exists.
7.3.3
Loss-of-Lock
When the PLL loses lock the PSR[LOCKS] status bit is set. If the PFDR is changed, or if an unexpected
loss of lock condition occurs, the LOCKS status bit is set. While the PLL is in an unlocked condition, the
system clocks continue to be sourced from the PLL as the PLL attempts to relock. Therefore, during the
re-locking process, the system-clock frequency is not well defined and may exceed the maximum system
frequency, violating the system clock timing specifications. Due to this condition, using the loss-of-lock
reset functionality as described in
the PLL has re-locked, the PLL does not update the PSR[LOCKS] status bit. The LOCKS status bit is
sticky, and the user must clear it before the PLL can write the register again.
Freescale Semiconductor
Section 7.3.3.1, "Loss of Lock Reset Request,"
MCF52277 Reference Manual, Rev. 1
Clock Module
is
recommended.
After
7-9
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