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Liquid Crystal Display Controller (LCDC)
21.3.12 LCDC PWM Contrast Control Register (LCD_PCCR)
The PWM contrast control register is used to control the signal output at the contrast pin, which controls
the contrast of the LCD panel.
Address: 0xFC0A_C02C (LCD_PCCR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-14. LCD PWM Contrast Control Register (LCD_PCCR)
Field
31–25
Reserved, must be cleared.
24–16
LCD_CLS high pulse width. Controls the pulse width of LCD_CLS in units of LCD_LSCLK. The actual pulse width
CLS_HI_
is CLS_HI_WDITH + 1.
WIDTH
15
LD mask. Enables/disables the line data (LCD_D[17:0]) output to zero for the Sharp TFT panel power-off sequence.
LDMSK
0 LCD_D[17:0] is normal.
1 LCD_D[17:0] always equals 0.
14–11
Reserved, must be cleared.
10–9
Source select. Selects the input clock source for the PWM counter. The PWM output frequency is equal to the
SCR
frequency of the input clock divided by 256.
00 Line pulse
01 Pixel clock
10 LCD clock (f
11 Reserved
8
Contrast control enable. Enables/disables the contrast control function.
CC_EN
0 Contrast control is off.
1 Contrast control is on.
7–0
Pulse width. Controls the pulse width of the built-in pulse width modulator, which controls the contrast of the LCD
PW
screen.
21.3.13 LCDC DMA Control Register (LCD_DCR)
There is a 32 × 32 bit line buffer in the LCDC that stores DMA data from system memory. The DMA
control register controls the DMA burst length and when to trigger a DMA burst in terms of the number
of data bytes left in the pixel buffer.
21-16
CLS_HI_WIDTH
Table 21-15. LCD_PCCR Field Descriptions
)
sys/2
MCF52277 Reference Manual, Rev. 1
15
14 13 12 11 10 9
0 0 0 0
LD
SCR
MSK
0
0 0 0 0 0 0
Description
Access: User read/write
8
7
6
5
4
3
2
1
CC_
PW
EN
0
0 0 0 0 0 0 0 0
Freescale Semiconductor
0
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