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Field
7–5
Reserved
4
Change of state (high-to-low or low-to-high transition).
COS
0 No change-of-state since the CPU last read UIPCRn. Reading UIPCRn clears UISRn[COS].
1 A change-of-state longer than 25–50 μs occurred on the UnCTS input. UACRn can be programmed to generate
an interrupt to the CPU when a change of state is detected.
3–1
Reserved
0
Current state of clear-to-send. Starting two serial clock periods after reset, CTS reflects the state of UnCTS. If
CTS
UnCTS is detected asserted at that time, COS is set, which initiates an interrupt if UACRn[IEC] is enabled.
0 The current state of the UnCTS input is asserted.
1 The current state of the UnCTS input is deasserted.
30.3.9
UART Auxiliary Control Register (UACRn)
The UACRs control the input enable.
Address: 0xFC06_0010 (UACR0)
0xFC06_4010 (UACR1)
0xFC06_8010 (UACR2)
7
R
W
0
Reset:
0
Field
7–1
Reserved, must be cleared.
0
Input enable control.
IEC
0 Setting the corresponding UIPCRn bit has no effect on UISRn[COS].
1 UISRn[COS] is set and an interrupt is generated when the UIPCRn[COS] is set by an external transition on the
UnCTS input (if UIMRn[COS] = 1).
30.3.10 UART Interrupt Status/Mask Registers (UISRn/UIMRn)
The UISRs, shown in
Figure
masked by UIMRn. If corresponding UISRn and UIMRn bits are set, internal interrupt output is asserted.
If a UIMRn bit is cleared, state of the corresponding UISRn bit has no effect on the output.
The UISRn and UIMRn registers share the same space in memory. Reading this register provides the user
with interrupt status, while writing controls the mask bits.
Freescale Semiconductor
Table 30-8. UIPCRn Field Descriptions
6
5
0
0
0
0
Figure 30-11. UART Auxiliary Control Registers (UACRn)
Table 30-9. UACRn Field Descriptions
30-12, provide status for all potential interrupt sources. UISRn contents are
MCF52277 Reference Manual, Rev. 1
Description
4
3
0
0
0
0
Description
UART Modules
Access: User write-only
2
1
0
0
IEC
0
0
0
0
30-13
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