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Field
3–2
SD_CLK slew rate mode. Controls the strength of the SD_CLK pin.
MSCR_
00 Half strength 1.8V low power/mobile DDR
SDCLK
01 Open drain
10 Full strength 1.8V low power/mobile DDR
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays
1–0
SD_A10, SD_CAS, SD_CKE, SD_CS1, SD_RAS, SD_SDR_DQS, SD_WE slew rate mode. Controls the strength
MSCR_
of the SDRAM control pins.
SDCTL
00 Half strength 1.8V low power/mobile DDR
01 Open drain
10 Full strength 1.8V low power/mobile DDR
11 2.5V DDR1 or 3.3V CMOS with roughly equal rise and fall delays
14.3.8
Drive Strength Control Registers (DSCR_x)
The drive strength control registers set the output pin drive strengths. All drive strength control registers
are read/write. These drive strength settings are effective in all non-JTAG modes, regardless of the current
functions of the pins.
Address: 0xFC0A_4048 (DSCR_DSPI)
0xFC0A_4049 (DSCR_TIMER)
0xFC0A_404A (DSCR_I2C)
0xFC0A_404B (DSCR_LCD)
0xFC0A_404C (DSCR_DEBUG)
0xFC0A_404E (DSCR_IRQ)
7
R
0
W
Reset:
0
Note: Reset state is dependent on the chosen reset configuration. See
Module (CCM),"
Address: 0xFC0A_404D (DSCR_CLKRST)
7
R
0
W
Reset:
0
Note: Reset state is dependent on the chosen reset configuration. See
Module (CCM),"
Figure 14-28. Clock/Reset Drive Strength Control Register (DSCR_CLKRST)
Freescale Semiconductor
Table 14-21. MSCR_SDRAM Field Descriptions (continued)
6
5
0
0
0
0
for details.
Figure 14-27. Drive Strength Control Registers (DSCR_x)
6
5
0
0
0
0
for details.
MCF52277 Reference Manual, Rev. 1
Description
4
3
2
0
0
0
0
0
0
4
3
2
0
DSE_RSTOUT
0
General Purpose I/O Module
Access: User read/write
1
0
DSE_x
See Note
Chapter 9, "Chip Configuration
Access: User read/write
1
0
DSE_FBCLK
See Note
Chapter 9, "Chip Configuration
14-25
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