Freescale Semiconductor MCF52277 Reference Manual page 287

Field
15–14 Bandwidth control. Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the
BWC eDMA processes the minor loop, it continuously generates read/write sequences until the minor count is
exhausted. This field forces the eDMA to stall after the completion of each read/write access to control the
bus request bandwidth seen by the crossbar switch (XBS).
00 No eDMA engine stalls
01 Reserved
10 eDMA engine stalls for 4 cycles after each r/w
11 eDMA engine stalls for 8 cycles after each r/w
Note: If the source and destination sizes are equal, this field is ignored between the first and second
transfers and after the last write of each minor loop. This behavior is a side effect of reducing start-up
latency.
13–12 Reserved, must be cleared.
11–8 Link channel number.
MAJOR_LINKCH If (MAJOR_E_LINK = 0) then
• No channel-to-channel linking (or chaining) is performed after the major loop counter is exhausted.
else
• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at the
channel defined by these four bits by setting that channel's TCDn_CSR[START] bit.
0–15 Link to DMA channel 0–15
7 Channel done. This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the
DONE CITER count reaches zero; The software clears it, or the hardware when the channel is activated.
Note: This bit must be cleared to write the MAJOR_E_LINK or E_SG bits.
6 Channel active. This flag signals the channel is currently in execution. It is set when channel service begins,
ACTIVE and the eDMA clears it as the minor loop completes or if any error condition is detected.
5 Enable channel-to-channel linking on major loop complete. As the channel completes the major loop, this
MAJOR_E_LINK flag enables the linking to another channel, defined by MAJOR_LINKCH. The link target channel initiates
a channel service request via an internal mechanism that sets the TCDn_CSR[START] bit of the specified
channel.
Note: To support the dynamic linking coherency model, this field is forced to zero when written to while the
TCDn_CSR[DONE] bit is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
4 Enable scatter/gather processing. As the channel completes the major loop, this flag enables scatter/gather
E_SG processing in the current channel. If enabled, the eDMA engine uses DLAST_SGA as a memory pointer to
a 0-modulo-32 address containing a 32-byte data structure loaded as the transfer control descriptor into the
local memory.
Note: To support the dynamic scatter/gather coherency model, this field is forced to zero when written to
while the TCDn_CSR[DONE] bit is set.
0 The current channel's TCD is normal format.
1 The current channel's TCD specifies a scatter gather format. The DLAST_SGA field provides a memory
pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
3 Disable request. If this flag is set, the eDMA hardware automatically clears the corresponding DMAERQ bit
D_REQ when the current major iteration count reaches zero.
0 The channel's DMAERQ bit is not affected.
1 The channel's DMAERQ bit is cleared when the major loop is complete.
Freescale Semiconductor
Table 17-30. TCDn_CSR Field Descriptions
MCF52277 Reference Manual, Rev. 1
Enhanced Direct Memory Access (eDMA)
Description
17-23