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Debug Module
Command Format:
15
14
13
0x2
Table 32-4
shows the definition of the DRc write encoding.
Command Sequence:
WDMREG
Operand Data:
Result Data:
32.6
Real-Time Debug Support
The ColdFire family provides support debugging real-time applications. For these types of embedded
systems, the processor must continue to operate during debug. The foundation of this area of debug support
is that while the processor cannot be halted to allow debugging, the system can generally tolerate the small
intrusions of the BDM inserting instructions into the pipeline with minimal effect on real-time operation.
The debug module provides four types of breakpoints: PC with mask, PC without mask, operand address
range, and data with mask. These breakpoints can be configured into one- or two-level triggers with the
exact trigger response also programmable. The debug module programming model can be written from the
external development system using the debug serial interface or from the processor's supervisor
programming model using the WDEBUG instruction. Only CSR is readable using the external
development system.
32.6.1
Theory of Operation
Breakpoint hardware can be configured through TDR[TCR] to respond to triggers by displaying DDATA,
initiating a processor halt, or generating a debug interrupt. As shown in
triggered, an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not displaying
captured processor status, operands, or branch addresses.
32-40
Figure 32-42.
WDMREG
12
11
10
9
0xC
MS DATA
???
'NOT READY'
XXX
'ILLEGAL'
Figure 32-43.
WDMREG
Longword data is written into the specified debug register. The data is supplied
most-significant word first.
Command complete status (0xFFFF) is returned when register write is complete.
MCF52277 Reference Manual, Rev. 1
BDM Command Format
8
7
6
5
100
D[31:16]
D[15:0]
LS DATA
'NOT READY'
'CMD COMPLETE'
NEXT CMD
'NOT READY'
Command Sequence
Table
4
3
2
1
DRc
NEXT CMD
32-24, when a breakpoint is
Freescale Semiconductor
0
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