Freescale Semiconductor MCF52277 Reference Manual page 600

Synchronous Serial Interface (SSI)
With the above conditions in normal mode with a continuous clock, each time the frame sync signal is
generated (or detected), a data word is clocked in. With the above conditions and a gated clock, each time
the clock begins, a data word is clocked in.
If receive FIFO 0 is not enabled, the received data word is transferred from the receive shift register
(RXSR) to the receive data register 0 (SSI_RX0), and the RDR0 flag is set. Receive interrupt 0 occurs if
the RIE and SSI_IER[RDR0] bits are set.
If receive FIFO 0 is enabled, the received data word is transferred to the receive FIFO 0. The RFF0 flag is
set if the receive data register (SSI_RX0) is full and receive FIFO 0 reaches the selected threshold. Receive
interrupt 0 occurs if RIE and SSI_IER[RFF0] bits are set.
The core has to read the data from the SSI_RX0 register before a new data word is transferred from the
RXSR; otherwise, receive overrun error 0 (ROE0) bit is set. If receive FIFO 0 is enabled, the ROE0 bit is
set when the receive FIFO 0 data level reaches the selected threshold and a new data word is ready to
transfer to the receive FIFO 0.
Figure 25-27 shows transmitter and receiver timing for an 8-bit word with two words per time slot in
normal mode and continuous clock with a late word length frame sync. The Tx data register is loaded with
the data to be transmitted. On arrival of the frame sync, this data is transferred to the transmit shift register
and transmitted on the SSI_TXD output. Simultaneously, the receive shift register shifts in the received
data available on the SSI_RXD input. At the end of the time slot, this data is transferred to the Rx data
register.
Continuous
SSI_BCLK
SSI_FS
Tx Data
SSI_TXD
SSI_RXD
Rx Data
Figure 25-28 shows a similar case for internal (SSI generates clock) gated clock mode, and
shows a case for external (SSI receives clock) gated clock mode.
A pull-down resistor is required in gated clock mode, because the clock port
is disabled between transmissions.
The Tx data register is loaded with the data to be transmitted. On arrival of the clock, this data transfers to
the transmit shift register and transmits on the SSI_TXD output. Simultaneously, the receive shift register
shifts in the received data available on the SSI_RXD input, and at the end of the time slot, this data
transfers to the Rx data register. In internal gated clock mode, the Tx data line and clock output port are
25-32
Figure 25-27. Normal Mode Timing - Continuous Clock
MCF52277 Reference Manual, Rev. 1
NOTE
Figure 25-29
Freescale Semiconductor