Introduction - Freescale Semiconductor MCF52277 Reference Manual

Chapter 3
ColdFire Core
3.1

Introduction

This section describes the organization of the Version 2 (V2) ColdFire
of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the
ColdFire Family Programmer's Reference Manual.
3.1.1 Overview
As with all ColdFire cores, the V2 ColdFire core is comprised of two separate pipelines decoupled by an
instruction buffer.
Instruction
Fetch
Pipeline
Operand
Execution
Pipeline
The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched
instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the
Freescale Semiconductor
Instruction
IAG Address
Generation
Instruction
IC
Fetch Cycle
FIFO
IB
Instruction Buffer
Decode & Select,
DSOC
Operand Fetch
Address
Generation,
AGEX
Execute
Figure 3-1. V2 ColdFire Core Pipelines
MCF52277 Reference Manual, Rev. 1
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processor core and an overview
Address [ :0]
31
Read Data[31:0]
Write Data[31:0]
3-1