Table of Contents
Advertisement
Cache
output of the storage array is driven onto the ColdFire core's local data bus, thereby completing the access
in a single cycle.
The tag array maintains a single valid bit per line entry. Accordingly, only entire 16-byte lines are loaded
into the cache.
The cache also contains separate 16-byte instruction and data line-fill buffers that provide temporary
storage for the last line fetched in response to a cache miss. With each fetch, the contents of the associated
line fill buffer are examined. Thus, each fetch address examines the tag memory array and the associated
line fill buffer to see if the desired address is mapped into either hardware resource. A cache hit in the
memory array or the associated line-fill buffer is serviced in a single cycle. Because the line fill buffer
maintains valid bits on a longword basis, hits in the buffer can be serviced immediately without waiting
for the entire line to be fetched.
If the referenced address is not contained in the memory array or the associated line-fill buffer, the cache
initiates the required external fetch operation. In most situations, this is a 16-byte line-sized burst
reference.
The hardware implementation is a nonblocking design, meaning the ColdFire core's local bus is released
after the initial access of a miss. Thus, the cache or the SRAM module can service subsequent requests
while the remainder of the line is being fetched and loaded into the fill buffer.
Local Address Bus
31
5.2
Memory Map/Register Definition
Three supervisor registers define the operation of the cache and local bus controller: the cache control
register (CACR) and two access control registers (ACR0, ACR1).
5-2
43
2
1
0
12
31
I or D Line
=
Fill Hit
31
Figure 5-1. 8-Kbyte Cache Block Diagram
MCF52277 Reference Manual, Rev. 1
4
I or D Line Buffer Storage
Buffer
Address
13
0
TAG
511
=
Tag Hit
Table 5-1
External Data[31:0]
MUX
31
0
0
DATA
2047
MUX
Local Data Bus
below shows the memory map
Freescale Semiconductor
Advertisement
Table of Contents
