Freescale Semiconductor MCF52277 Reference Manual page 660

DMA Serial Peripheral Interface (DSPI)
Field
30–27 Frame size. Selects the number of bits transferred per frame. The FMSZ field is used in master mode and slave
FMSZ mode. The table below lists the frame sizes.
26 Clock polarity. Selects the inactive state of the serial communications clock (DSPI_SCK). This bit is used in master
CPOL and slave mode. For successful communication between serial devices, the devices must have identical clock
polarities. When the continuous selection format is selected (CONT or DCONT is set), switching between clock
polarities without stopping the DSPI can cause errors in the transfer due to the peripheral device interpreting the
switch of clock polarity as a valid clock edge. For more information on continuous selection format, refer to
Section 29.4.4.5, "Continuous Selection
0 The inactive state value of DSPI_SCK is low
1 The inactive state value of DSPI_SCK is high
25 Clock phase. Selects which edge of DSPI_SCK causes data to change and which edge causes data to be captured.
CPHA This bit is used in master and slave mode. For successful communication between serial devices, the devices must
have identical clock phase settings.
Note: When the continuous selection format is selected (CONT or DCONT is set), switching between clock phases
without stopping the DSPI can cause errors in the transfer.
0 Data is captured on the leading edge of DSPI_SCK and changed on the following edge
1 Data is changed on the leading edge of DSPI_SCK and captured on the following edge
24 LSB first enable. Selects if the LSB or MSB of the frame is transferred first. This bit is only used in master mode.
LSBFE 0 Data is transferred MSB first
1 Data is transferred LSB first
23–22 PCS to SCK delay prescaler. Selects the prescaler value for the delay between assertion of DSPI_PCS and the first
PCSSCK edge of the DSPI_SCK. This field is only used in master mode.
Note: When the continuous selection format is selected (CONT or DCONT is set), switching the PCS to SCK delay
prescaler without stopping the DSPI can cause errors in the transfer.
Note: See Section 29.4.3.2, "PCS to SCK Delay
00 1 clock DSPI_PCS to DSPI_SCK delay prescaler
01 3 clock DSPI_PCS to DSPI_SCK delay prescaler
10 5 clock DSPI_PCS to DSPI_SCK delay prescaler
11 7 clock DSPI_PCS to DSPI_SCK delay prescaler
29-10
Table 29-5. DSPI_CTARn Field Description (continued)
FMSZ Framesize
0000 Reserved
0001 Reserved
0010 Reserved
0011 4
0100 5
0101 6
0110 7
0111 8
Format."
MCF52277 Reference Manual, Rev. 1
Description
FMSZ
1000
1001
1010
1011
1100
1101
1110
1111
(tCSC)," for details on calculating the PCS to SCK delay.
Framesize
9
10
11
12
13
14
15
16
Freescale Semiconductor