Device Data Structures - Freescale Semiconductor MCF52277 Reference Manual

To initialize the host controller, software must:
1. Optionally set streaming disable in the USBMODE[SDIS] bit.
2. Optionally modify the BURSTSIZE register.
3. Optionally write the appropriate value to the USBINTR register to enable the desired interrupts.
4. Set the USBMODE[CM] field to enable host mode, and set the USBMODE[ES] bit for big endian
operation.
5. Write the USBCMD register to set the desired interrupt threshold, frame list size (if applicable),
and turn the controller on by setting the USBCMD[RS] bit.
6. Enable external VBUS supply. The exact steps required for initialization depend on the external
hardware used to supply the 5V VBUS power.
7. Set the PORTSC[PP] bit.
At this point, the host controller is up and running and the port registers begin reporting device connects.
System software can enumerate a port through the reset process (port is in the enabled state).
To communicate with devices via the asynchronous schedule, system software must write the
ASYNCLISTADDR register with the address of a control or bulk queue head. Software must then enable
the asynchronous schedule by setting the asynchronous schedule enable (ASE) bit in the USBCMD
register. To communicate with devices via the periodic schedule, system software must enable the periodic
schedule by setting the periodic schedule enable (PSE) bit in the USBCMD register. Schedules can be
turned on before the first port is reset and enabled.
Any time the USBCMD register is written, system software must ensure the appropriate bits are preserved,
depending on the intended operation.
20.5.2

Device Data Structures

This section defines the interface data structures used to communicate control, status, and data between
device controller driver (DCD) software and the device controller.The interface consists of device queue
heads and transfer descriptors.
Software must ensure that data structures do not span a 4K-page boundary.
The USB OTG uses an array of device endpoint queue heads to organize device transfers. As shown in
Figure 20-38, there are two endpoint queue heads in the array for each device endpoint—one for IN and
one for OUT. The EPLISTADDR provides a pointer to the first entry in the array.
Freescale Semiconductor
NOTE
MCF52277 Reference Manual, Rev. 1
Universal Serial Bus Interface – On-The-Go Module
20-47