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Enhanced Direct Memory Access (eDMA)
Address: 0xFC04_401B (EDNA_CEEI)
7
R
0
W
Reset
0
Figure 17-10. eDMA Clear Enable Error Interrupt Register (EDMA_CEEI)
Field
7
Reserved, must be cleared.
6
Clear all enable error interrupts.
CAEE
0 Clear only those EDMA_EEI bits specified in the CEEI field.
1 Clear all bits in EDMA_EEI.
5–4
Reserved, must be cleared.
3–0
Clear enable error interrupt. Clears the corresponding bit in EDMA_EEI.
CEEI
17.6.9
eDMA Clear Interrupt Request Register (EDMA_CINT)
The EDMA_CINT provides a simple, memory-mapped mechanism to clear a given bit in the EDMA_INT
to disable the interrupt request for a given channel. The given value on a register write causes the
corresponding bit in the EDMA_INT to be cleared. Setting the CAIR bit provides a global clear function,
forcing the entire contents of the EDMA_INT to be cleared, disabling all DMA interrupt requests. Reads
of this register return all zeroes.
Address: 0xFC04_401C (EDMA_CINT)
7
R
0
W
Reset
0
Field
7
Reserved, must be cleared.
6
Clear all interrupt requests.
CAIR
0 Clear only those EDMA_INT bits specified in the CINT field.
1 Clear all bits in EDMA_INT.
17-12
6
5
0
0
CAEE
0
0
Table 17-11. EDMA_CEEI Field Descriptions
6
5
0
0
CAIR
0
0
Figure 17-11. eDMA Clear Interrupt Request (EDMA_CINT)
Table 17-12. EDMA_CINT Field Descriptions
MCF52277 Reference Manual, Rev. 1
4
3
0
0
0
0
Description
4
3
0
0
0
0
Description
Access: User write-only
2
1
0
CEEI
0
0
Access: User write-only
2
1
0
CINT
0
0
Freescale Semiconductor
0
0
0
0
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