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The following table indicates the status of the SSI_ISR[TFE0/1] flag, with different settings of the
SSI_FCSR[TFWM0/1] bits and varying amounts of data in the Tx FIFO.
Table 25-14. Status of Transmit FIFO Empty Flag (SSI_ISR[TFEn])
25.3.14 SSI AC97 Control Register (SSI_ACR)
SSI_ACR controls various features of the SSI operating in AC97 mode.
Address: 0xFC0B_C038 (SSI_ACR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
31–11
Reserved, must be cleared.
10–5
Frame rate divider. Controls the frequency of AC97 data transmission/reception. This field is programmed with the
FRDIV
number of frames for which the SSI should be idle after operating in one frame. Through these bits, the AC97
frequency of operation, from 48 KHz (000000) to 1 KHz (101111) can be achieved.
E.g: 001010 (10 Decimal) equals SSI operates once every 11 frames.
4
Write command. Specifies whether the next frame carries an AC97 write command or not. When this bit is set, the
WR
corresponding tag bits (corresponding to command address and command data slots of the next transmit frame) are
automatically set. The SSI automatically clears this bit after completing transmission of a frame.
0 Next frame does not have a write command
1 Next frame does have a write command
Note: Do not set WR and RD at the same time.
Freescale Semiconductor
Transmit FIFO
Watermark (TFWMn)
0
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
Figure 25-21. SSI AC97 Control Register (SSI_ACR)
Table 25-15. SSI_ACR Field Descriptions
MCF52277 Reference Manual, Rev. 1
Number of data in the Tx FIFO
1
2
3
4
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
Description
Synchronous Serial Interface (SSI)
6
7
8
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access: User read/write
8
7
6
5
4
3
2
FRDIV
WR RD TIF FV AC97EN
0
0
0
1
0
0
0
25-27
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