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Field
4
Pen down flag. Indicates a pen-down event has occurred. This flag is sticky and is cleared by writing a 1 to it.
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Clearing this bit is processed asynchronously.
0 Pen down not detected
1 Pen down detected
3
Reserved, must be cleared.
2
Pen FIFO programmable level flag. Indicates the sample FIFO level has matched the value in
PFLF
ASP_ICR[FIFO_WM]. Reading data out of the FIFO so the FIFO level is less than the value in FIFO_WM clears
PFLF automatically.
0 Pen FIFO has not reached the level programmed in FIFO_WM
1 Pen FIFO has reached the level programmed in FIFO_WM
1
Pen FIFO full flag. Indicates the sample FIFO is full. Reading data out of the FIFO so the FIFO is not full clears
PFFF
PFFF automatically.
0 Pen FIFO is not full
1 Pen FIFO full
Note: Although setting PFFF is immediate, there is a maximum of a two ADC_CLK cycle delay from FIFO
changes to this bit clearing. Therefore, it is suggested not to use this bit during normal operation, but as
a mechanism for error handling.
0
Pen data ready flag. Indicates at least one valid sample is available in the pen sample FIFO. Emptying the FIFO
PDRF
by reading all samples in it clears this bit automatically.
0 The pen sample FIFO is empty
1 One or more samples available in the pen sample FIFO
Note: Although clearing PDRF is immediate after reading out the last sample in the FIFO, there is a maximum
of a two internal bus clocks (f
22.3.6
ASP Sample FIFO (ASP_SFIFO)
The ASP sample FIFO holds the sample data after A/D sampling. The data sequence is controlled by the
setting of ASP_CR. This register supports only the lower 16-bit and 32-bit read accesses. Write accesses,
upper 16-bit, and byte read accesses result in a transfer error.
The ASP sample FIFO is read-only. After reset, the FIFO is empty and
reading the FIFO results in an undefined value.
Address: 0xFC0A_8014 (ASP_SFIFO)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 U U U U U U U U U U U U U U U U
Freescale Semiconductor
Table 22-7. ASP_ISR Field Descriptions (continued)
) delay from FIFO changes to this bit setting.
sys/2
Figure 22-7. ASP Sample FIFO Register (ASP_SFIFO)
MCF52277 Reference Manual, Rev. 1
Touchscreen Controller/Analog-to-Digital Converter
Description
NOTE
CHANID
Access: User read/write
8
7
6
5
4
3
2
1
0
SAMPLE
22-11
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