Freescale Semiconductor MCF52277 Reference Manual page 601

tri-stated at the end of transmission of the last bit (at the completion of the complete clock cycle). Whereas,
in external gated clock mode, the Tx data line is tri-stated at the last inactive edge of the incoming bit clock
(during the last bit in a data word).
Gated
SSI_BCLK
Tx Data
SSI_TXD
SSI_RXD
Rx Data
Gated
SSI_BCLK
Tx Data
SSI_TXD
SSI_RXD
Rx Data
25.4.1.2 Network Mode
Network mode creates a time division multiplexed (TDM) network, such as a TDM codec network or a
network of DSPs. In continuous clock mode, a frame sync occurs at the beginning of each frame. In this
mode, the frame is divided into more than one time slot. During each time slot, one data word can be
transferred (rather than in the frame sync time slot as in normal mode). Each time slot is then assigned to
an appropriate codec or DSP on the network. The processor can be a master device that controls its own
private network or a slave device connected to an existing TDM network and occupies a few time slots.
The frame rate dividers, controlled by the DC bits, select two to thirty-two time slots per frame. The length
of the frame is determined by:
• The period of the serial bit clock (PSR, PM bits for internal clock, or the frequency of the external
clock on the SSI_BCLK pin)
• The number of bits per sample (WL bits)
• The number of time slots per frame (DC bits)
Freescale Semiconductor
Figure 25-28. Normal Mode Timing - Internal Gated Clock
Figure 25-29. Normal Mode Timing - External Gated Clock
MCF52277 Reference Manual, Rev. 1
Synchronous Serial Interface (SSI)
25-33