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Universal Serial Bus Interface – On-The-Go Module
20.5.3
Device Operation
The device controller performs data transfers using a set of linked list transfer descriptors pointed to by a
queue head. The next sections explain the use of the device controller from the device controller driver
(DCD) point-of-view and further describe how specific USB bus events relate to status changes in the
device controller programmer's interface.
20.5.3.1
Device Controller Initialization
After hardware reset, USB OTG is disabled until the run/stop bit in the USBCMD register is set. At
minimum, it is necessary to have the queue heads set up for endpoint 0 before the device attach occurs.
Shortly after the device is enabled, a USB reset occurs followed by setup packet arriving at endpoint 0. A
queue head must be prepared so the device controller can store the incoming setup packet.
To initialize a device, the software must:
1. Optionally set streaming disable in the USBMODE[SDIS] bit.
2. Optionally modify the BURSTSIZE register.
3. Write the appropriate value to the USBINTR to enable the desired interrupts. For device operation,
setting UE, UEE, PCE, URE, and SLE is recommended.
For a list of available interrupts, refer to
(USBINTR),"
4. Set the USBMODE[CM] field to enable device mode, and set the USBMODE[ES] bit for big
endian operation.
5. Optionally write the USBCMD register to set the desired interrupt threshold.
6. Set USBMODE[SLOM] to disable setup lockouts.
7. Initialize the EPLISTADDR.
8. Create two dQHs for endpoint 0—one for IN transactions and one for OUT transactions.
For information on device queue heads, refer to
9. Set the CCM's UOCSR[BVLD] bit to allow device to connect to a host.
10. Set the USBCMD[RS] bit.
After the run/stop bit is set, a device reset occurs. The DCD must monitor the reset event and set the
DEVICEADDR and EPCRn registers, and adjust the software state as described in
"Bus Reset."
Endpoint 0 is a control endpoint only and does not need to configured using
the EPCR0 register.
It is not necessary to initially prime endpoint 0 because the first packet received is always a setup packet.
The contents of the first setup packet requires a response in accordance with USB device framework
command set.
20-54
and
Section 20.3.4.2, "USB Status Register (USBSTS)."
MCF52277 Reference Manual, Rev. 1
Section 20.3.4.3, "USB Interrupt Enable Register
Section 20.5.2.1, "Endpoint Queue Head."
NOTE
Section 20.5.3.2.1,
Freescale Semiconductor
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