Freescale Semiconductor MCF52277 Reference Manual page 436

Universal Serial Bus Interface – On-The-Go Module
20.5.5.6 Miscellaneous Variations from EHCI
20.5.5.6.1 Programmable Physical Interface Behavior
The modules support multiple physical interfaces that can operate in different modes when the module is
configured with the software programmable physical interface modes. The control bits for selecting the
PHY operating mode are added to the PORTSCn register providing a capability not defined by the EHCI
specification.
20.5.5.6.2 Discovery
Port Reset
The port connect methods specified by EHCI require setting the port reset bit in the PORTSCn register for
a duration of 10 ms. Due to the complexity required to support the attachment of devices not high speed,
a counter is present in the design that can count the 10 ms reset pulse to alleviate the requirement of the
software to measure this duration. Therefore, the basic connection is summarized as:
• Port change interrupt—Port connect change occurs to notify the host controller driver that a device
has attached.
• Software shall set the PORTSCn[PR] bit to reset the device.
• Software shall clear the PORTSCn[PR] bit after 10 ms.
— This step, necessary in a standard EHCI design, may be omitted with this implementation.
Should the EHCI host controller driver attempt to write a 0 to the reset bit while a reset is in
progress, the write is ignored and the reset continues until completion.
• Port change interrupt—Port enable change occurs to notify the host controller that the device is
now operational and at this point the port speed is determined.
Port Speed Detection
After the port change interrupt indicates that a port is enabled, the EHCI stack should determine the port
speed. Unlike the EHCI implementation, which re-assigns the port owner for any device that does not
connect at high speed, this host controller supports direct attach of non-HS devices. Therefore, the
following differences are important regarding port speed detection:
• Port owner hand-off is not implemented. Therefore, PORTSCn[PO] bit is read-only and always
reads 0.
• A 2-bit port speed indicator field has been added to PORTSCn to provide the current operating
speed of the port to the host controller driver.
• A 1-bit high-speed indicator bit has been added to PORTSCn to signify that the port is in HS vs.
FS/LS.
— This information is redundant with the 2-bit port speed indicator field above.
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MCF52277 Reference Manual, Rev. 1
Freescale Semiconductor