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DMA Serial Peripheral Interface (DSPI)
For queued operations, the SPI queues reside in system RAM external to the DSPI. Data transfers between
the queues and the DSPI FIFOs are accomplished through the use of a DMA controller or through host
software.
The pin multiplexing and control module must be configured to enable the
peripheral function of the appropriate pins (refer to
Purpose I/O
29.1.3
Features
The DSPI supports these SPI features:
•
Full-duplex, three-wire synchronous transfers
•
Master and slave mode
•
Buffered transmit and receive operation using the TX and RX FIFOs, with depths of 16 entries
•
Visibility into TX and RX FIFOs for ease of debugging
•
FIFO bypass mode for low-latency updates to SPI queues
•
Programmable transfer attributes on a per-frame basis
— Eight clock and transfer attribute registers
— Serial clock with programmable polarity and phase
— Programmable delays
– PCS to SCK delay
– SCK to PCS delay
– Delay between frames
— Programmable serial frame size of 4 to 16 bits, expandable with software control
— Continuously held chip select capability
•
Three peripheral chip selects, expandable to 8 with external demultiplexer
•
Two DMA conditions for SPI queues residing in RAM or Flash
— TX FIFO is not full (TFFF)
— RX FIFO is not empty (RFDF)
•
Eight interrupt conditions
– End of queue reached (EOQF)
– TX FIFO is not full (TFFF)
– Transfer of current frame complete (TCF)
– FIFO underflow (slave only, the slave is asked to transfer data when the TX FIFO is empty)
(TFUF)
– RX FIFO is not empty (RFDF)
– FIFO overflow (attempt to transmit with an empty TX FIFO or serial frame received while
RX FIFO is full) (RFOF)
– FIFO overrun (logical OR of RX overflow and TX underflow interrupts)
29-2
NOTE
Module") prior to configuring the DSPI.
MCF52277 Reference Manual, Rev. 1
Chapter 14, "General
Freescale Semiconductor
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