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14.3
Memory Map/Register Definition
Table 14-4
summarizes all the registers in the ports address space.
Address
0xFC0A_4000 PODR_BE
0xFC0A_4001 PODR_CS
0xFC0A_4002 PODR_FBCTL
0xFC0A_4003 PODR_I2C
0xFC0A_4005 PODR_UART
0xFC0A_4006 PODR_DSPI
0xFC0A_4007 PODR_TIMER
0xFC0A_4008 PODR_LCDCTL
0xFC0A_4009 PODR_LCDDATAH
0xFC0A_400A PODR_LCDDATAM
0xFC0A_400B PODR_LCDDATAL
0xFC0A_400C PDDR_BE
0xFC0A_400D PDDR_CS
0xFC0A_400E PDDR_FBCTL
0xFC0A_400F PDDR_I2C
0xFC0A_4011 PDDR_UART
0xFC0A_4012 PDDR_DSPI
0xFC0A_4013 PDDR_TIMER
0xFC0A_4014 PDDR_LCDCTL
0xFC0A_4015 PDDR_LCDDATAH
0xFC0A_4016 PDDR_LCDDATAM
0xFC0A_4017 PDDR_LCDDATAL
0xFC0A_4018 PPDSDR_BE
0xFC0A_4019 PPDSDR_CS
0xFC0A_401A PPDSDR_FBCTL
0xFC0A_401B PPDSDR_I2C
Freescale Semiconductor
Table 14-4. GPIO Module Memory Map
Register
Port Output Data Registers
Port Data Direction Registers
Port Pin Data/Set Data Registers
MCF52277 Reference Manual, Rev. 1
General Purpose I/O Module
Width
Access Reset Value
(bits)
8
R/W
0x0F
8
R/W
0x0F
8
R/W
0x0F
8
R/W
0x03
8
R/W
0xFF
8
R/W
0x0F
8
R/W
0x0F
8
R/W
0x0F
8
R/W
0x03
8
R/W
0xFF
8
R/W
0xFF
8
R/W
0x00
8
R/W
0x00
8
R/W
0x00
8
R/W
0x00
8
R/W
0x00
8
R/W
0x00
8
R/W
0x00
8
R/W
0x00
8
R/W
0x00
8
R/W
0x00
8
R/W
0x00
8
R/W
See Section
8
R/W
See Section
8
R/W
See Section
8
R/W
See Section
Section/Page
14.3.1/14-11
14.3.1/14-11
14.3.1/14-11
14.3.1/14-11
14.3.1/14-11
14.3.1/14-11
14.3.1/14-11
14.3.1/14-11
14.3.1/14-11
14.3.1/14-11
14.3.1/14-11
14.3.2/14-12
14.3.2/14-12
14.3.2/14-12
14.3.2/14-12
14.3.2/14-12
14.3.2/14-12
14.3.2/14-12
14.3.2/14-12
14.3.2/14-12
14.3.2/14-12
14.3.2/14-12
14.3.3/14-13
14.3.3/14-13
14.3.3/14-13
14.3.3/14-13
14-9
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