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25.2
External Signal Description
The five SSI signals are explained below.
Name
SSI_CLKIN
SSI_BCLK
SSI_MCLK
SSI_FS
SSI_RXD
SSI_TXD
25.2.1
SSI_CLKIN — SSI Clock Input
The SSI module can be clocked by the internal core frequency derived from the PLL or this input clock.
The source is selected by the MISCCR[SSISRC] bit in the CCM. See
Module (CCM),"
and
25.2.2
SSI_BCLK — Serial Bit Clock
This input or output signal is used by the transmitter and receiver and can be continuous or gated. During
gated clock mode, data on the SSI_BCLK port is valid only during the transmission of data; otherwise, it
is pulled to the programmed inactive state.
25.2.3
SSI_MCLK — Serial Master Clock
This clock signal is output from the device when it is the master. When in I
referred to as the oversampling clock. The frequency of SSI_MCLK is a multiple of the frame clock.
25.2.4
SSI_FS — Serial Frame Sync
The input or output frame sync is used by the transmitter and receiver to synchronize the transfer of data.
The frame sync signal can be one bit or one word in length and can occur one bit before the transfer of data
or right at the transfer of data. In gated clock mode, the frame sync signal is not used. If SSI_FS is
configured as an input, the external device should drive SSI_FS during rising edge of SSI_BCLK.
25.2.5
SSI_RXD — Serial Receive Data
The SSI_RXD port is an input and brings serial data into the receive data shift register.
25.2.6
SSI_TXD — Serial Transmit Data
The SSI_TXD port is an output and transmits data from the serial transmit shift register. The SSI_TXD
port is an output port when data is transmitted and disabled between data word transmissions and on the
trailing edge of the bit clock after the last bit of a word is transmitted.
Freescale Semiconductor
Table 25-2. Signal Properties
Function
SSI Clock Input
Serial Bit Clock
Serial Master Clock
Serial Frame Sync
Serial Receive Data
Serial Transmit Data
Figure
25-37.
MCF52277 Reference Manual, Rev. 1
Synchronous Serial Interface (SSI)
Direction
Reset State
I
I
I/O
0
O
0
I/O
0
I
—
O
0
Chapter 9, "Chip Configuration
2
S master mode, this signal is
Pull up
Passive
Passive
Passive
Passive
—
Passive
25-5
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