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Field
14–12
Precharge to active delay. Precharge command to following active command delay counter.
PRE2ACT
Suggested value = (t
Example:
If t
= 20ns and f
RP
Suggested value = (20ns × 99MHz) - 1 = 0.98; round to 1.
Note: Count value is in SD_CLK periods for SDR and DDR modes.
11–8
Refresh to active delay. Refresh command to following active or refresh command delay counter.
REF2ACT
SDR/DDR: REF2ACT = (t
Example (for SDR/DDR):
If t
RFC
Suggested value = (75ns × 99MHz) - 1 = 6.425; round to 7.
Note: Count value is in SD_CLK periods for SDR and DDR modes.
7
Reserved, must be cleared.
6–4
Write latency. Write command to write data delay counter.
WT_LAT
SDR: write 0x0
DDR: write 0x3
Note: SDR mode: Count value is in SD_CLK periods.
DDR mode: Count value is in SD_CLK2 periods.
3–0
Reserved, must be cleared.
19.4.4
SDRAM Configuration Register 2 (SDCFG2)
The 32-bit read/write configuration register 2 stores delay values necessary between specific SDRAM
commands. During initialization, software loads values to the register according to the SDRAM
information obtained from the data sheet. This register is reset only by a power-up reset signal.
The burst length (BL) field must be exact. All other fields govern the relative timing from one command
to another, they have minimum values but any larger value is also legal (but with decreased performance).
All delays in this register are expressed in SD_CLK. In all calculations for setting the fields of this register,
convert time units to clock units and round up to the nearest integer.
Address: 0xFC0B_800C (SCFG2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
BRD2RP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Freescale Semiconductor
Table 19-9. SDCFG1 Field Descriptions (continued)
× f
) - 1 (Round up to nearest integer)
RP
SD_CLK
= 99MHz
SD_CLK
× f
) - 1 (Round up to nearest integer)
RFC
SD_CLK
= 75ns and f
= 99MHz
SD_CLK
BWT2RWP
BRD2W
Figure 19-8. SDRAM Configuration Register 2 (SDCFG2)
MCF52277 Reference Manual, Rev. 1
Description
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BL
SDRAM Controller (SDRAMC)
Access: User read/write
8
7
6
5
4
3
2
1
0
19-19
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