Functional Description - Freescale Semiconductor MCF52277 Reference Manual

Interrupt Controller Modules
15.3

Functional Description

15.3.1 Interrupt Controller Theory of Operation
To support the interrupt architecture of the 68K/ColdFire programming model, the 64 interrupt sources are
organized as 7 levels, with an arbitrary number of requests programmed to each level. The priority
structure within a single interrupt level depends on the interrupt source number assignments (see
Section 15.2.9.1, "Interrupt
numbered interrupt source. See the below table for an example.
The level is fully programmable for all sources. The 3-bit level is defined in the interrupt control register
(ICR0n, ICR1n).
The operation of the interrupt controller can be broadly partitioned into three activities:
• Recognition
• Prioritization
• Vector determination during IACK
15.3.1.1 Interrupt Recognition
The interrupt controller continuously examines the request sources (IPRn) and the interrupt mask register
(IMRn) to determine if there are active requests. This is the recognition phase. The interrupt force register
(INTFRCn) also factors into the generation of an active request.
15.3.1.2 Interrupt Prioritization
As an active request is detected, it is translated into the programmed interrupt level. Next, the appropriate
level masking is performed if this feature is enabled. The level of the active request must be greater than
the current mask level before it is signaled in the processor. The resulting unmasked decoded priority level
is driven out of the interrupt controller. The decoded priority levels from the interrupt controllers are
logically summed together, and the highest enabled interrupt request is sent to the processor core during
this prioritization phase.
15.3.1.3 Interrupt Vector Determination
After the core has sampled for pending interrupts and begun interrupt exception processing, it generates
an interrupt acknowledge cycle (IACK). The IACK transfer is treated as a memory-mapped byte read by
15-16
Sources"). The higher numbered interrupt source has priority over the lower
Table 15-18. Example Interrupt Priority Within a Level
Interrupt Source
40
22
8
2
MCF52277 Reference Manual, Rev. 1
ICR[2:0]
011
011
011
011
Priority
Highest
Lowest
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