Free-Running Timer Operation - Freescale Semiconductor MCF52277 Reference Manual

Programmable Interrupt Timers (PIT0–PIT1)
When the PCSRn[OVW] bit is set, the counter can be directly initialized by writing to PMRn without
having to wait for the count to reach 0x0000.
PIT CLOCK
COUNTER
MODULUS
PIF
27.3.2

Free-Running Timer Operation

This mode of operation is selected when the PCSRn[RLD] bit is clear. In this mode, the counter rolls over
from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement.
When the counter reaches a count of 0x0000, PCSRn[PIF] flag is set. If the PCSRn[PIE] bit is set, PIF flag
issues an interrupt request to the CPU.
When the PCSRn[OVW] bit is set, counter can be directly initialized by writing to PMRn without having
to wait for the count to reach 0x0000.
PIT CLOCK
COUNTER
MODULUS
PIF
27.3.3 Timeout Specifications
The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the internal
bus clock period as selected by the PCSRn[PRE] bits. The PMRn[PM] bits select the timeout period.
Timeout period
27.3.4 Interrupt Operation
Table 27-6 shows the interrupt request generated by the PIT.
27-6
0x0002 0x0001
Figure 27-5. Counter Reloading from the Modulus Latch
0x0002 0x0001
Figure 27-6. Counter in Free-Running Mode
= PRE[3:0]
MCF52277 Reference Manual, Rev. 1
0x0000
0x0005
0x0000
0x0005
×
(PM[15:0] + 1)
×
f
sys 2 ⁄
0x0005
0xFFFF
Eqn. 27-1
Freescale Semiconductor