Freescale Semiconductor MCF52277 Reference Manual page 317

Figure 18-9 shows the write cycle timing diagram.
The address and data busses are muxed between the FlexBus and SDRAM
controller. At the end of the write bus cycles the address signals are
indeterminate.
FB_CSn, FB_BE/BWEn
18.4.5.3 Bus Cycle Sizing
This section shows timing diagrams for various port size scenarios.
read transfer to an 8-bit device with no wait states. The address is driven on the FB_A[
throughout the bus cycle. The external device returns the read data on FB_D[31:24] and may tristate the
data line or continue driving the data one clock after FB_TA is sampled asserted.
FB_D[31:24]
FB_CSn, FB_OE,
FB_BE/BWEn
Freescale Semiconductor
S0
FB_CLK
FB_A[23:0]
FB_D[31:X]
ADDR[31:X]
FB_R/W
FB_TS
FB_OE
FB_TA
Figure 18-9. Basic Write-Bus Cycle
S0
FB_CLK
FB_A[23:0]
ADDR[31:24]
FB_R/W
FB_TS
FB_TA
Figure 18-10. Single Byte-Read Transfer
MCF52277 Reference Manual, Rev. 1
NOTE
S1 S2
ADDR[23:0]
DATA
Figure 18-10
S1 S2 S3
ADDR[23:0]
DATA[7:0]
S3 S0
illustrates the basic byte
23:8
S0
FlexBus
] bus
18-15