Table of Contents
Advertisement
22.3.8
ASP Clock Divider Register (ASP_CLKD)
ASP_CLKD controls the divider for the ADC clock (nominally 2 MHz). The delays controlled by the bit
fields in the ASP_TIM register are counted in ticks of the clock generated by this divisor (nominally 0.5 μs
when the ADC clock is 2 MHz).
Address: 0xFC0A_801C (ASP_CLKD)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1
Field
31–7
Reserved, must be cleared.
6–0
ASP clock divider. The ASP clock is derived using the following formulas.
If 15 ≤ CLKD ≤ 127:
CLKD
If 1 ≤ CLKD ≤ 14 and CLKD is even:
If 1 ≤ CLKD ≤ 14 and CLKD is odd:
The clock divider supports odd and even numbers of divisors for the clock. When an odd number is specified,
the high-time count is one count larger than the low count. This produces an asymmetric clock for all odd counts.
Take care when using an odd divider to ensure the duty cycle of the ASP clock does not exceed 60%. This is
generally a problem when the internal bus clock frequency (f
To avoid duty cycle issues, the divider automatically adjusts small odd divider settings. When the divide ratio of
(CLKD + 1) is odd and less than 16, the nearest smaller even setting is used. For example, when the CLKD
setting is six, before the automatic adjusting, the ADC_CLK frequency is
is 57.14%. After the automatic adjusting, the ADC_CLK frequency is
50%.
Note: When ASP_CLKD is set to zero, the ADC_CLK signal is disabled.
22.4
Function Description
The analog signal processor may be configured as a touchscreen or generic ADC depending on
ASP_CR[TSE]. If set, the module is configured as a touchscreen controller; if cleared, the module is
configured as general purpose ADC.
Freescale Semiconductor
Figure 22-9. ASP Clock Divide Register (ASP_CLKD)
Table 22-10. ASP_CLKD Field Descriptions
f
ASP
f
ASP
f
ASP
MCF52277 Reference Manual, Rev. 1
Touchscreen Controller/Analog-to-Digital Converter
Description
f
sys/2
=
------------------------ -
CLKD
+
1
f
sys/2
=
--------------- -
CLKD
f
sys/2
=
------------------------ -
CLKD
+
1
) is less than ~8 MHz.
sys/2
1
/
of the bus clock and the duty cycle is
6
Access: User read/write
8
7
6
5
4
3
2
CLKD
1
/
of the bus clock and the duty cycle
7
1
0
Eqn. 22-3
Eqn. 22-4
Eqn. 22-5
22-13
Advertisement
Table of Contents
