Freescale Semiconductor MCF52277 Reference Manual page 402

Universal Serial Bus Interface – On-The-Go Module
Field
19–18 TX endpoint type.
TXT 00 Control
01 Isochronous
10 Bulk
11 Interrupt
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should
be configured as a bulk type endpoint.
17 TX endpoint data source. This bit should always be written as 0, which selects the dual port memory/DMA engine
TXD as the source.
16 TX endpoint stall. This bit sets automatically upon receipt of a SETUP request if this endpoint is not configured as
TXS a control endpoint. It clears automatically upon receipt of a SETUP request if this endpoint is configured as a
control endpoint.
Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host. It continues
returning STALL until software clears this bit clears or automatically clears as above.
0 Endpoint OK
1 Endpoint stalled
15–8 Reserved, must be cleared.
7 RX endpoint enable.
RXE 0 Disabled
1 Enabled
6 RX data toggle reset. When a configuration event is received for this endpoint, software must write a 1 to this bit
RXR to synchronize the data PIDs between the host and device. This bit is self-clearing.
5 RX data toggle inhibit. This bit is only for testing and should always be written as 0. Writing a 1 to this bit causes
RXI this endpoint to ignore the data toggle sequence and always accept data packets regardless of their data PID.
0 PID sequencing enabled
1 PID sequencing disabled
4 Reserved, must be cleared.
3–2 RX endpoint type.
RXT 00 Control
01 Isochronous
10 Bulk
11 Interrupt
Note: When only one endpoint (RX or TX, but not both) of an endpoint pair is used, the unused endpoint should
be configured as a bulk type endpoint.
1 RX endpoint data sink. This bit should always be written as 0, which selects the dual port memory/DMA engine
RXD as the sink.
0 RX endpoint stall. This bit sets automatically upon receipt of a SETUP request if this endpoint is not configured
RXS as a control endpoint. It clears automatically upon receipt of a SETUP request if this endpoint is configured as a
control endpoint,
Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host. It continues
returning STALL until software clears this bit or automatically clears as above,
0 Endpoint OK
1 Endpoint stalled
20-44
Table 20-41. EPCRn Field Descriptions (continued)
MCF52277 Reference Manual, Rev. 1
Description
Freescale Semiconductor