Freescale Semiconductor MCF52277 Reference Manual page 555

Internal Bus
Clock (f )
sys/2
24.3.1.1 Prescaled Clock (A or B)
The internal bus clock is the input clock to the PWM prescaler that can be disabled when the device is in
debug mode by setting the PWMCTL[PFRZ] bit. This is useful for reducing power consumption and for
emulation to freeze the PWM. The input clock is also disabled when all PWM channels are disabled
(PWMEn=0).
Clock A and B are scaled values of the input clock. The value is software selectable for clock A and B and
has options of 1, 1/2,..., or 1/128 times the internal bus clock. The value selected for clock A and B is
determined by the PWMPRCLK[PCKAn] and PWMPRCLK[PCKBn] bits.
Freescale Semiconductor
PWMSCLA
PWMPRCLK
[PCKA]
PWMSCLB
PWMPRCLK
[PCKB]
Figure 24-14. PWM Clock Select Block Diagram
MCF52277 Reference Manual, Rev. 1
Pulse-Width Modulation (PWM) Module
PCLR1
Clock SA
÷2
Clock Clock A
PCLR5
PCLR2
Clock SB
÷2
Clock B
PCLR7
PCLR0
1
Clock to
PWM0
0
1
Clock to
PWM1
0
PCLR4
1
Clock to
PWM4
0
1
Clock to
PWM5
0
1
Clock to
PWM2
0
1
Clock to
PWM3
0
PCLR3
PCLR6
1
Clock to
PWM6
0
1
Clock to
PWM7
0
24-13