Freescale Semiconductor MCF52277 Reference Manual page 608

Synchronous Serial Interface (SSI)
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When I S modes are entered (SSI_CR[I2S] = 01 or 10), these settings are recommended:
• Synchonous mode (SSI_CR[SYN] = 1)
• Tx shift direction: msb transmitted first (SSI_TCR[TSHFD] = 0)
• Rx shift direction: msb received first (SSI_RCR[RSHFD] = 0)
• Tx data clocked at falling edge of the clock (SSI_TCR[TSCKP] = 1)
• Rx data latched at rising edge of the clock (SSI_RCR[RSCKP] = 1)
• Tx frame sync active low (SSI_TCR[TFSI] = 1)
• Rx frame sync active low (SSI_RCR[RFSI] = 1)
• Tx frame sync initiated one bit before data is transmitted (SSI_TCR[TEFS] = 1)
• Rx frame sync initiated one bit before data is received (SSI_RCR[REFS] = 1)
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25.4.1.4.1 I S Master Mode
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In I S master mode (SSI_CR[I2S] = 01), these additional settings are recommended:
• Internal generated bit clock (SSI_TCR[TXDIR] = 1)
• Internal generated frame sync (SSI_TCR[TFDIR] = 1)
The processor automatically performs these settings when in I
• Network mode is selected (SSI_CR[NET] = 1)
• Tx frame sync length set to one-word-long-frame (SSI_TCR[TFSL] = 0)
• Rx frame sync length set to one-word-long-frame (SSI_RCR[RFSL] = 0)
• Tx shifting w.r.t. bit 0 of TXSR (SSI_TCR[TXBIT0] = 1)
• Rx shifting w.r.t. bit 0 of RXSR (SSI_RCR[RXBIT0] = 1)
Set the SSI_CCR[PM, PSR, DIV2, WL, DC] control bits to configure the bit clock and frame sync.
The word length is fixed to 32 in I
contain valid data (out of the 32 transmitted/received bits in each channel). The fixing of word duration as
32 simplifies the relation between oversampling clock (SSI_MCLK) and the frame sync (SSI_MCLK
becomes an integer multiple of frame sync). The period of the oversampling clock must be at least 4x the
internal bus clock period.
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25.4.1.4.2 I S Slave Mode
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In I S slave mode (SSI_CR[I2S] = 10), the following additional settings are recommended:
• External generated bit clock (SSI_TCR[TXDIR] = 0)
• External generated frame sync (SSI_TCR[TFDIR] = 0)
25-40
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S master mode, and the WL bits determine the number of bits that
MCF52277 Reference Manual, Rev. 1
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S master mode:
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